Full chip scan provide logic that links EVERY flipflop in a design into one or more scan chain (not just boundary scan which checks pin bonding) - mostly it's a

Full chip scan provide logic that links EVERY flipflop in a design into one or more scan chain (not just boundary scan which checks pin bonding) - mostly it's a mux on each input - and is more like 5%ish You test by scanning in a bit pattern, issuing a single clock andscanning out the result. Smart software generates the minimal set of test vectors that tests every wire and gate between the flops. Chip testers are expensive (millionish) so minimising tester time minimises chip cost - we make special testign logic for things like srams