3 ms·
When I was studying EE, a professor said on this subject that about 20% of the transistors in a chip are used for self-diagnostics. Manufacturing failures are a
by intrasight 11y ago
When I was studying EE, a professor said on this subject that about 20% of the transistors in a chip are used for self-diagnostics. Manufacturing failures are a given. The diagnostics tell the company what has failed, and they segment the chips into different product/price classes based upon what works and what doesn't. After being deployed into a product, I assume that chips would follow a standard Bathtub Curve: https://en.wikipedia.org/wiki/Bathtub_curve https://en.wikipedia.org/wiki/Bathtub_curve
As geometries fall, the effects of "wear" at the atomic level will go up.
- pjc50 11y agoI think the proportion is nowhere near that high for most ASICs - JTAG boundary scan adds a few percent to give you this testability, maybe 1-5%.
- Taniwha 11y agoFull chip scan provide logic that links EVERY flipflop in a design into one or more scan chain (not just boundary scan which checks pin bonding) - mostly it's a mux on each input - and is more like 5%ish You test by scanning in a bit pattern, issuing a single clock andscanning out the result. Smart software generates the minimal set of test vectors that tests every wire and gate between the flops. Chip testers are expensive (millionish) so minimising tester time minimises chip cost - we make special testign logic for things like srams
- panax 11y agoYour dual core CPU is often the same quad core die with two of the cores disabled because one of the cores has a defect and is sold at a discount to increase yield.