4 ms·

Hi Will, A recurring question by the audience in the talks is that you will not get many benefits from such a wide architecture on general purpose code because

by Robi395 11y ago

Hi Will, A recurring question by the audience in the talks is that you will not get many benefits from such a wide architecture on general purpose code because of there is not enough "available parallelism". Do you have any concrete code examples where the Mill will find stuff to do where a OOO will not?

willvarfar 11y ago
There are lots of small ways we can get more units in use more of the time. ILP is a bit of a misnomer on the Mill as each Mill instruction contains many operations and these execute in 'phases' over the subsequent cycles. In the extreme(ly common) case you have a single-instruction tight loop but the second phase of the first iteration is running as the first phase of the second iteration runs. Mind-bending. We have more success at speculation than a mainstream machine as we have cheap null and `None` propagation; see http://millcomputing.com/topic/metadata/ http://millcomputing.com/topic/metadata/ And as the Mill is a belt machine, and as the hardware manages the call stack, the units can be in use by the caller even when the PC is in the callee. If you schedule, say, a `multiply` that takes 4 cycles and then next cycle call into a function (which usually takes just a cycle) then the machine can go run the function, however long it takes. When the function returns that `multiply` has long since completed but the spiller is going to use result replay to drop the results on the belt at the right time. A lot of time is spent in loops, though, and the Mill does really well at those! On the Mill, all levels of loop can be pipelined because each level of loop is given its own call frame, allowing the result replay to work. See http://millcomputing.com/topic/pipelining/ http://millcomputing.com/topic/pipelining/ Sorry for linking to just so many of the talks! ;)
- Robi395 11y ago
  Thanks, I'll take a look at those links. In the meantime, I have another question. How much do the Mill team plan to share with the general public before any product release, can we expect a emulator, it would be great to toy with.
  - willvarfar 11y ago
    We are planning to release the simulator and LLVM-based compiler real soon.
    - Frenchgeek 11y ago
      So since I'm completely over my head here : Will you name the simulator Don Quixote or Sancho Panza? ( And... tails, so I have to submit this. Sorry! )
- reinoud 11y ago
  I am curious why you folks didn't go the RISC-V route (open source) and create a new architecture for all to use and expand? With patents etc. i fear the Mill is going the Tilera route and won't be heared much from in a couple of years. Interesting concept though!
  - CyberDildonics 11y ago
    It seems to me that the whole point of the company is to create patents and demonstrate that they are valuable.
    - reinoud 11y ago
      If you have working prototypes and a community to collaborate them, getting funds for actual testing it in silicon is not that hard esp. not if you collaborate with an University. With good performing silicon one can then expand and the folks who designed it are garanteed to have a job updating and enhancing it for the next 10 years or more :) Esp. if other companies sponser their work. Are the Mills creators afraid say Intel will use their ideas and create their own chips excluding them from business? ARM itself is beaten by RISC-V's initial Rocket prototypes in power and area and the upcomming BOOMs are a good match for ARM Cortex A15+ (only 64 bit). And they only recently started just with OoO chips. And do you see ARM suddenly creating RISC-V chips? or borrowing their ideas?

by Robi395 11y ago

willvarfar 11y ago

There are lots of small ways we can get more units in use more of the time. ILP is a bit of a misnomer on the Mill as each Mill instruction contains many operations and these execute in 'phases' over the subsequent cycles. In the extreme(ly common) case you have a single-instruction tight loop but the second phase of the first iteration is running as the first phase of the second iteration runs. Mind-bending. We have more success at speculation than a mainstream machine as we have cheap null and `None` propagation; see http://millcomputing.com/topic/metadata/ http://millcomputing.com/topic/metadata/ And as the Mill is a belt machine, and as the hardware manages the call stack, the units can be in use by the caller even when the PC is in the callee. If you schedule, say, a `multiply` that takes 4 cycles and then next cycle call into a function (which usually takes just a cycle) then the machine can go run the function, however long it takes. When the function returns that `multiply` has long since completed but the spiller is going to use result replay to drop the results on the belt at the right time. A lot of time is spent in loops, though, and the Mill does really well at those! On the Mill, all levels of loop can be pipelined because each level of loop is given its own call frame, allowing the result replay to work. See http://millcomputing.com/topic/pipelining/ http://millcomputing.com/topic/pipelining/ Sorry for linking to just so many of the talks! ;)

Robi395 11y ago
Thanks, I'll take a look at those links. In the meantime, I have another question. How much do the Mill team plan to share with the general public before any product release, can we expect a emulator, it would be great to toy with.
- willvarfar 11y ago
  We are planning to release the simulator and LLVM-based compiler real soon.
  - Frenchgeek 11y ago
    So since I'm completely over my head here : Will you name the simulator Don Quixote or Sancho Panza? ( And... tails, so I have to submit this. Sorry! )
reinoud 11y ago
I am curious why you folks didn't go the RISC-V route (open source) and create a new architecture for all to use and expand? With patents etc. i fear the Mill is going the Tilera route and won't be heared much from in a couple of years. Interesting concept though!
- CyberDildonics 11y ago
  It seems to me that the whole point of the company is to create patents and demonstrate that they are valuable.
  - reinoud 11y ago
    If you have working prototypes and a community to collaborate them, getting funds for actual testing it in silicon is not that hard esp. not if you collaborate with an University. With good performing silicon one can then expand and the folks who designed it are garanteed to have a job updating and enhancing it for the next 10 years or more :) Esp. if other companies sponser their work. Are the Mills creators afraid say Intel will use their ideas and create their own chips excluding them from business? ARM itself is beaten by RISC-V's initial Rocket prototypes in power and area and the upcomming BOOMs are a good match for ARM Cortex A15+ (only 64 bit). And they only recently started just with OoO chips. And do you see ARM suddenly creating RISC-V chips? or borrowing their ideas?