3 ms·
Probably to drive the memory LCD. The drive timing in the datasheet looks pretty tight (about 2.2MHz), and bit banging at that rate will leave the uC unable to
by ctz 11y ago
Probably to drive the memory LCD. The drive timing in the datasheet looks pretty tight (about 2.2MHz), and bit banging at that rate will leave the uC unable to much else during a screen update. Ideally, you want to make use of the STM32F439's 2D graphics accelerator to do graphics legwork, then the DMA controller to write out to the screen.
The FPGA could even have been provided by the LCD vendor to provide a more standard interface.
- quadrature 11y agoMaybe, I would figure that a driver would be baked into the LCD module so the processor writes to a buffer and it picks it up on the next tick.
- ctz 11y agoReplying to myself: this was actually confirmed by one of the developers on reddit: https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebble_time_teardown/crnr78a?context=10000 https://www.reddit.com/r/pebble/comments/37lg95/ifixit_pebbl...