Pretty much every deep OoO design is going to have uops inside. Look at the A15 here, for instance: http://regmedia.co.uk/2011/10/20/arm_a15_pipeline_large.jp

Pretty much every deep OoO design is going to have uops inside. Look at the A15 here, for instance: http://regmedia.co.uk/2011/10/20/arm_a15_pipeline_large.jpg http://regmedia.co.uk/2011/10/20/arm_a15_pipeline_large.jpg On ARM most of your splitting is going to be breaking out the predication so that the scheduler only has to work with 2 input uops. The thing about x86 is that the instruction stream isn't self-synchronizing, it's hard and occasionally impossible to figure out where the instruction boundaries are if you don't decode progressively from the front. This means that to decode mulitple instructions per clock cycle x86 has to use complicated voodoo.