4 ms·

* 24 "tiles" with two IA cores per tile * A 24-router mesh network with 256 GB/s bisection bandwidth * 4 integrated DDR3 memory controllers * Hardware sup

by yu 17y ago

* 24 "tiles" with two IA cores per tile * A 24-router mesh network with 256 GB/s bisection bandwidth * 4 integrated DDR3 memory controllers * Hardware support for message-passing IA x86 compatible. Availability not announced. Experimental.