3 ms·
Verilator only supports a synthesizable subset of verilog, so if you want to write a testbench you are either going to be writing it with synthesizable verilog
by krupan 11y ago
Verilator only supports a synthesizable subset of verilog, so if you want to write a testbench you are either going to be writing it with synthesizable verilog (not recommended) or with C++ (or something else you figure out how to link in).
- jeffbush 11y agoThe main thing it is missing is delays (it does have non-synthesizable constructs like $display). However, if you're developing a processor, most of your testing is executing programs. For that, you don't need a complex testbench: just load the executable code into your memory and toggle the clock.