4 ms·
I use Verilog, so I'm not as familiar with the state of VHDL tools. I've found Verilator to be much faster (although it cuts some corners) than the free version
by jeffbush 11y ago
I use Verilog, so I'm not as familiar with the state of VHDL tools. I've found Verilator to be much faster (although it cuts some corners) than the free versions of Modelsim. It's fairly stable and supports most of the core synthesizable SystemVerilog constructs.
- sliverstorm 11y agoIn my experience if you want to do much HDL development, it is a good idea to just bite the bullet and build a fast workstation. Some tools are faster than others, but eventually as your design grows they are all slow. At least then you can use whatever tool you please.
- krupan 11y agoVerilator only supports a synthesizable subset of verilog, so if you want to write a testbench you are either going to be writing it with synthesizable verilog (not recommended) or with C++ (or something else you figure out how to link in).
- jeffbush 11y agoThe main thing it is missing is delays (it does have non-synthesizable constructs like $display). However, if you're developing a processor, most of your testing is executing programs. For that, you don't need a complex testbench: just load the executable code into your memory and toggle the clock.