4 ms·
What about floor-planning or post place-and-route netlist viewing? Some things are pretty hard to do without the vendor's tools. Also, Xilinx tools are universe
by blackguardx 11y ago
What about floor-planning or post place-and-route netlist viewing? Some things are pretty hard to do without the vendor's tools. Also, Xilinx tools are universely renowned for being terrible, but Altera's toolchain can be pretty decent. It at least approaches the quality a 90s programmer would expect.
- jeffbush 11y agoYou know, I've personally never needed to use the floor-planning tools. It seems like a pretty advanced option. Of course, using open source simulators/command line flow doesn't preclude opening the floor planning tool in the GUI when you need it (my command line based synthesis flow just invokes the same tools that the GUI does). I find the post place-and-route netlist viewer inscrutable. I have debugged some synthesis issues by generating the post synthesis simulation model in Verilog and digging through that in a text editor. Maybe that's a weird way to do it, but I find it much faster and easier, especially when I know the signal names I'm looking for. My main problem is with the Altera GUI tools. It's a personal preference thing obviously, but I'm pretty attached to my editor, as are most people.
- sliverstorm 11y agoI don't know if this is what your parent meant, but you don't need those things if you never map the design to hardware. Which, though a good learning experience, isn't a necessity in learning about basic CPU architecture.