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Forgive my ignorance, for I'm just starting out with VHDL and digital hardware design in general. Building a CPU is what I eventually intend to do and I am cur
by gshrikant 11y ago
Forgive my ignorance, for I'm just starting out with VHDL and digital hardware design in general.
Building a CPU is what I eventually intend to do and I am curious how would you benchmark a hardware design?
What metrics would someone use for judging the effectiveness of a CPU arch? My current understanding is gate count, area occupied by the design, clocks per instruction (CPI) and maximum frequency the design can be clocked at.
- snops 11y agoA common metric in embedded is DMIPS/MHz. This is considered a bit antiquated (first written for the VAX!), but the Dhrystone benchmark is free and simple to implement. The important part is that its (supposedly) independent of clock speed to show the efficiency of your CPU design, and so is normally run from cache to get zero wait-states. CoreMark[1] is a new replacement, and is becoming increasingly popular. Once you implement/simulate your design in silicon, power usage becomes a good comparison metric. As the depends on clock frequency, DMIPS/mW is another common comparison benchmark. Since a lot of embedded applications spend most of there time in very low power states with the core stopped, sleep current and wake/sleep time are now becoming very important. This is more of a whole chip benchmark, and is a very popular area for microcontroller manufacturers to fight over right now, as results can vary wildly depending on the application. The makers of CoreMark have tried to come out with a benchmark[2], but it doesn't cover peripherals yet and isn't quite as popular. 1. https://www.eembc.org/coremark/ https://www.eembc.org/coremark/ 2. http://www.eembc.org/ulpbench/ http://www.eembc.org/ulpbench/