And this is what you can use if you want to implement an instruction or two in Verilog without having to implement the rest of the CPU. Plus a flexible compiler

And this is what you can use if you want to implement an instruction or two in Verilog without having to implement the rest of the CPU. Plus a flexible compiler toolchain: https://github.com/combinatorylogic/soc https://github.com/combinatorylogic/soc (never mind it being multicycle, it was done this way for a reason, and dropping in a RISC design should be fairly trivial.)