And read the design guidelines from the FPGA vendor of the device you are targeting. Xilinx, Altera (Intel), Microsemi and Cypress all have different rules for

And read the design guidelines from the FPGA vendor of the device you are targeting. Xilinx, Altera (Intel), Microsemi and Cypress all have different rules for mapping things like memories, write enables etc. Xilinx is happy to not reset registers, Altera will generate a bigger design if reset is not stated in the code.