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I started doing serious FPGA work (VHDL development) the last months and finally get a little knowledgeable on how to properly architect a design of medium comp
by cnvogel 11y ago
I started doing serious FPGA work (VHDL development) the last months and finally get a little knowledgeable on how to properly architect a design of medium complexity so that it properly works at non trivial clock speeds. (after mainly doing trivialities before)
So far the learning experience was great, and generally the best about learning new things for me isn't so much when I get something finished (the last steps often become a tedious chore). Rather I most enjoy working on a (for me, at this point) hard problem and finally get the flash of understanding when a initially misunderstood error or bug can be explained... Luckily the world of programmable logic seems to have no shortage of hard to comprehend things 😁.
But I think that should be everyone's motivation to learn new things, right?