3 ms·
I remember a post a few years ago about running code by triggering page faults in the MMU. Basically they created a single instruction computer (which can be Tu
by smegel 11y ago
I remember a post a few years ago about running code by triggering page faults in the MMU. Basically they created a single instruction computer (which can be Turing complete) out of the MMU, hence allowing processing to occur with the MMU that is invisible to the CPU and everything else. I wonder if related.
http://en.wikipedia.org/wiki/One_instruction_set_computer http://en.wikipedia.org/wiki/One_instruction_set_computer
- jbangert 11y ago(author here) https://github.com/jbangert/trapcc https://github.com/jbangert/trapcc We did get a few hypervisor crashes and the Intel architecture has all sorts of subtle behaviour that is often not modelled properly. It would be good to see someone build on my work.