3 ms·
I recently wrote a place and route tool for Lattice iCE40 FPGAs [0]. The bitstream was reverse engineered by Clifford Wolf and others as part of the IceStorm p
by cottonseed 11y ago
I recently wrote a place and route tool for Lattice iCE40 FPGAs [0]. The bitstream was reverse engineered by Clifford Wolf and others as part of the IceStorm project [1]. We're using Yosys [2] for Verilog synthesis, also written by Clifford.
[0] https://github.com/cseed/arachne-pnr https://github.com/cseed/arachne-pnr
[1] http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
[2] http://www.clifford.at/yosys/ http://www.clifford.at/yosys/
- FullyFunctional 11y agoWow, that is pretty awesome. I didn't expect this to have arrived that quickly. Does it support user constraints on relative placement (and routing)? Self-timed logic, such as NULL Convention Logic [1], doesn't fit well with the synchronous FPGA paradigm, but can be implement on those if the feedback loops are tightly controlled [2]. I'd like to play with that :) [1] http://en.wikipedia.org/wiki/Asynchronous_circuit http://en.wikipedia.org/wiki/Asynchronous_circuit http://www.amazon.com/Designing-Asynchronous-Circuits-Convention-Synthesis/dp/1598299816 [2] http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5438673&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5438673 http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=543867...
- cottonseed 11y agoWhoa, I had no idea you could do async circuits on an FPGA (although I can't get to [2] right now, the site is under maintenance). Right now, I only support IO constraints. The IceStorm project hasn't documented the timing model yet but it is in pipeline. Is it possible to do what you want with vendor tools? Anyways, email me and we can chat about what you'd need.