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The next (obvious) question: What's gonna happen w/ Xilinx. For the longest time, the FPGA market has been dominated by Xilinx and Altera. With one joining In

• m_mueller 11y ago
  I'm thinking it could be interesting for Nvidia, considering that they have been building up HPC as their second leg, as an insurance policy in case Intel invests heavily into tooling and process technology for FPGA. Plus they're in a partnership with IBM now, who probably have some interesting use cases for future FPGAs (i.e. deep learning).
• bryanlarsen 11y ago
  While this is obviously a win for Altera: they gain the Intel process advantage; this deal does have a number of advantages for Xilinx: - Altera will now likely lose early access to all the non-Intel fabs. And sometimes one of the non-Intel fabs come up with a process advantage before Intel does. Fabs love to work with FPGA vendors: the regular structure makes them good targets for new processes; and FPGA vendors are the only people that can sell a single chip for $50,000. - Big guys are only interested in big markets: Altera may abandon some of the smaller niches they currently play in. I'm sure there are other advantages Xilinx gains by staying independent.
  • minthd 11y ago
    >> Fabs love to work with FPGA vendors: the regular structure makes them good targets for new processes I heard that this has changed and mobile chips are being used for "pipe cleaning" in fabs, from a credible source, but i haven't dug into the details of how.
• aswanson 11y ago
  I hope the develop open and cheap compilation tools to force xilinx to do the same.
  • bjackman 11y ago
    I believe the Xilinx tools are actually free of cost. Still, though, open source FPGA tools are desperately needed. edit: even if they just opened up the bitfile format. I believe it's a similar situation as GPU instructions sets though: managers saying "no because patents".
    • cottonseed 11y ago
      I recently wrote a place and route tool for Lattice iCE40 FPGAs [0]. The bitstream was reverse engineered by Clifford Wolf and others as part of the IceStorm project [1]. We're using Yosys [2] for Verilog synthesis, also written by Clifford. [0] https://github.com/cseed/arachne-pnr https://github.com/cseed/arachne-pnr [1] http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/ [2] http://www.clifford.at/yosys/ http://www.clifford.at/yosys/
      • FullyFunctional 11y ago
        Wow, that is pretty awesome. I didn't expect this to have arrived that quickly. Does it support user constraints on relative placement (and routing)? Self-timed logic, such as NULL Convention Logic [1], doesn't fit well with the synchronous FPGA paradigm, but can be implement on those if the feedback loops are tightly controlled [2]. I'd like to play with that :) [1] http://en.wikipedia.org/wiki/Asynchronous_circuit http://en.wikipedia.org/wiki/Asynchronous_circuit http://www.amazon.com/Designing-Asynchronous-Circuits-Convention-Synthesis/dp/1598299816 [2] http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5438673&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5438673 http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=543867...
        • cottonseed 11y ago
          Whoa, I had no idea you could do async circuits on an FPGA (although I can't get to [2] right now, the site is under maintenance). Right now, I only support IO constraints. The IceStorm project hasn't documented the timing model yet but it is in pipeline. Is it possible to do what you want with vendor tools? Anyways, email me and we can chat about what you'd need.
• phkahler 11y ago
  >> The next (obvious) question: What's gonna happen w/ Xilinx. Altera will have a process advantage over Xilinx and there is nothing that can be done about it. While everyone is talking 14nm, Intel is shipping it and talking 10nm. This deal makes more sense than any I've seen. Altera gets to use the best fabs in the world to gain an advantage over their competitors. Intel gets to deploy to a new (to them) market where the volumes are lower but the ASPs are higher - this is good given the ever increasing costs of making chips and the lower yields likely at 10nm and 7nm. It looks like a purely strategic move for both companies.
  • weland 11y ago
    I'd be curious to see just how long it will take Altera to adopt such a fine process for FPGA cells though. Edit: ha! Apparently, "One reason why Altera is attractive to Intel is that Altera is already using Intel's fab to create its latest generation FPGAs and SoCs; Arria 10 FPGAs and SoCs are being implemented using TSMC's 20nm process, while Stratix 10 FPGAs and SoCs are leveraging Intel’s 14 nm Tri-Gate process (see Altera & Intel to Collaborate on Multi-Die 14nm FPGAs). Furthermore, Altera is also using Intel's state-of-the-art packaging technologies." http://www.eetimes.com/document.asp?doc_id=1326736&_mc=sm_eet http://www.eetimes.com/document.asp?doc_id=1326736&_mc=sm_ee...
    • CHY872 11y ago
      FPGAs have a lot of very regular structures, so they're generally one of the first things you produce with a process.
      • sliverstorm 11y ago
        Probably easier to design too, allowing you to tape out your process launch vehicle early.
• fnordfnordfnord 11y ago
  Heard something about Avago the other day. http://seekingalpha.com/news/2530316-xilinx-up-after-new-intel-altera-report-avago-a-potential-suitor http://seekingalpha.com/news/2530316-xilinx-up-after-new-int...
• anontera 11y ago
  Basically, they're fucked. Altera's next chip was going to wipe the floor with Xilinx anyways. Xilinx has better tools, but they are going to be in trouble now that they are behind in process. They'll get acquired by someone, probably in a year or two. If they lose their market leadership in the meantime, the acquisition will be for less than 17B. They really need to invest in their software and tool flow right now. That's where they have a strong lead.