There is a difference between formal specification and formal verification. Formal specification is what we have with TLA+: you create a high-level description

There is a difference between formal specification and formal verification. Formal specification is what we have with TLA+: you create a high-level description of your system, to which you apply software tools to check the design. It's like blueprints for software. Formal verification deals with proving that the actual code you write implements a formal specification. This is a much, much harder problem. Usually, it involves cajoling a theorem prover by adding lots of annotations to your code. There's been some impressive work with the Ironclad project from MSR[1] which brought this down to ~5 lines of annotation per single line of implementation code - within striking distance of unit testing! Still, probably a decade or more away from widespread use. Formal verification isn't quite what you meant, though. You were talking about code generation. For general systems specified by TLA+, this isn't going to be useful unless you write in a very idiomatic way; in which case TLA+ is just a very high-level programming language. However, code generation is implemented in some specification languages that deal with very specific areas of system design. I'm thinking primarily of the P language[2], which is used to specify & check state machines and includes code generation capabilities for C++ and C#. [1] https://www.usenix.org/conference/osdi14/technical-sessions/presentation/hawblitzel https://www.usenix.org/conference/osdi14/technical-sessions/... [2] http://research.microsoft.com/apps/pubs/default.aspx?id=177118 http://research.microsoft.com/apps/pubs/default.aspx?id=1771...