It's quite possible that in SPEC benchmarks they used 2 Elbrus cores and 1 Pentium M core, so IPCs are about the same. And it's confirmed by 7zip benchmark. In

It's quite possible that in SPEC benchmarks they used 2 Elbrus cores and 1 Pentium M core, so IPCs are about the same. And it's confirmed by 7zip benchmark. In theory Elbrus can dispatch 23 non-SIMD ops per cycle, it has only 6 integer units and 4 among them can do FP, so it's not clear what remaining 17 operations can do. Modern x86 CPUs have about the same number of integer/FP ALUs. Current IPC is quite good, but it's hard to tell if core clock can be increased without lowering IPC. If ALU pipelines are short, it may be difficult to increase frequency without adding more stages. If more stages are added then pipeline flushes due to unpredicted jumps will result in heavier penalty. And it looks like Elbrus doesn't have a branch predictor at all. Pipeline stalls caused by memory access will also increase with CPU frequency. In x86 CPUs they are somewhat masked by out-of-order execution and SMT, which Elbrus doesn't have, so it should depend on memory preload instructions inserted by compiler.