Latches are caught by the synthesis tools generally. Designers usually run a unconstrained synthesis as a matter of course to determine whether they have writte

Latches are caught by the synthesis tools generally. Designers usually run a unconstrained synthesis as a matter of course to determine whether they have written junk. As for the other bugs, I look forward to this new paradigm of spotting them early without verification effort. Reasoning about transactions is already how verification works. It is transaction based. UVM is a library of SystemVerilog classes aimed at abstracting the verification to higher levels. Check out: https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1c/html/files2/intro-txt.html https://verificationacademy.com/verification-methodology-ref... We build over these classes to create our test benches.