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A Look at Altera's OpenCL SDK for FPGAs
- aylons 12y agoLots of interest about FPGA in HN lately. I wonder what caused this spark.
- mmastrac 12y agoIMO: FPGAs are an interesting beast because they've been inaccessible to a lot of people thanks to the poor and/or expensive tooling and development boards. That's starting to change slowly and people are getting interested in trying something new.
- aylons 12y agoWell, good development boards are cheaper nowadays, Vivado is slightly better than ISE, but pro tools are still very expensive and, of course, terrible. Actually, most discussions here in HN are about how bad FPGA tools are.
- manis404 12y agoIntel is buying Xilinx, the largest FPGA manufacturer... Why is everyone going DEEP?!:( I thought I could just run my javascript code in a java based browser running in a java VM running inside a VM written in Python. :( WE NEED MORE HIGH LEVEL STUFF. Not VHDL and whatnot. Coz the hardware will always be 'fast enough', right?
- kregasaurusrex 12y agoI'm a CS major switching to EE and it's a logical intersection of the two fields, but hasn't recieved the same amount of attention and hype as the rest of the IoT movement.
- aswanson 12y agoWhy are you switching to EE? The most interesting questions EE can address are in the CS domain. EE is the past, CS is the future. CS is to EE as Architecture is to knowing how to use a hammer, nails, and a saw. And I say this as an MSEE.
- be5invis 12y agoSeriously, I am using it to create an open-source quantum mechanics software, supports both GPU and FPGA acceleration.
- PascLeRasc 12y agoReport back here when you do, please.
- CthulhuOvermind 12y agoInteresting to see this here. I did my masters thesis on this sdk the past September. We compared a neural network in native C to a CPU opencl implementation, and a FPGA implementation. The FPGA had about 8-10 times the kernel performance of a i7-2600k for the task. Interesting enough, what caused the jump in performance was the capability to have memory close to the kernel, with enough capacity to handle the kernel demands. The CPU was capped on what the ram-cpu bandwidth was, around 21gigs, however, the slower pci-e FPGA did not suffer, because of FPGA implemented memory could hold the necessary data at hand. Hence I sent the data to the kernel asynchronously, then a kernel with around 120 parallel implementations would operate and feed back the data through pci-e. Having OpenCl certainly reduced dev time by around 85% id say. And that's from someone fluent with verilog, who didn't know openCL before doing this.
- manis404 12y agoCare to mention in what field you did your bachelors and masters? You got into FPGAs though CS or through EE? I'm always curious about FPGA engineers.
- CthulhuOvermind 12y agoHeya, did my undegrads as EE, changed it halfway from a 4 year MENG course to a 3 year bachelors because I was bored of the power distribution related stuff. Went on to do a masters in Advanced Microelectronics Design. I had contact with FPGA's in both my undergrad and my masters. I selected my BENG thesis on an ARM M0 soft implementation on an FPGA that implemented an expanded instruction set with increased performance on the SHA-1 algorithm.
- minthd 12y agoHow efficiently OpenCl used the FPGA ? And BTW, i remember reading some paper that compared CPU/GPU/FPGA. The conclusion was - GPU's win on compute/$, FPGA's win on compute/watt. Hard to find the paper now, though.
- manis404 12y ago