There's a second performance reason (although I can't comment on whether it's relevant in this case); it's cache banking. Sandy Bridge and Ivy Bridge processor

There's a second performance reason (although I can't comment on whether it's relevant in this case); it's cache banking. Sandy Bridge and Ivy Bridge processors load data into L1 cache in 64 byte chunks. This is split across 8 banks, the first 8 bytes go in the first bank, and so on. Each bank can service one request at a time. If you have aligned structs, then you will only be accessing one cache bank for each request. If you have unaligned structs, you might access two cache banks, or three for a 16 byte read. This increases contention and reduces the opportunities for instruction level parallelism, because it increases the number of conflicting instructions. This is unfortunately tricky to benchmark synthetically (your link displayed it well; his benchmark doesn't show it but the linked benchmark is 50% slower - who's is the realistic case? (probably a bit of both)), but it's entirely possible that you'd see a difference over a large test case set. I think with Haswell there's less of a problem. Also it's probably easier for them to align and guarantee their code works on all architectures; PHP memory usage is not huge in general (I know Wordpress is doing badly if it uses 64MB) so it's not really a problem.