Considering the Parallela cores are pretty basic RISC processors anyway and have a ton of shared memory, you probably don't want to treat them as regular Erlang

Considering the Parallela cores are pretty basic RISC processors anyway and have a ton of shared memory, you probably don't want to treat them as regular Erlang nodes regardless. Still, this is hardly a "drop-in" scale kind of thing. It's more like... having an FPGA with some nice glue you can call out to.