The µop cache was new in Sandy Bridge, but earlier Intel and AMD micro-architectures had a loop buffer that served decoded macro-ops for tight loops, bypassing

The µop cache was new in Sandy Bridge, but earlier Intel and AMD micro-architectures had a loop buffer that served decoded macro-ops for tight loops, bypassing fetch and decode (in earlier designs still, it only bypassed fetch). IIRC ARM added a 32-entry loop buffer with Cortex-A15. Not sure about later designs.