3 ms·

I don't think you understand how this works at all. It's like when you add a few cortex m0's to your phone, and now you have a quad-core phone. (It's 8 issue.

I don't think you understand how this works at all. It's like when you add a few cortex m0's to your phone, and now you have a quad-core phone. (It's 8 issue. You can issue 8 instructions to it, it just doesn't process them all in a single cycle :P)

sliverstorm 12y ago
8-issue means you can issue 8 things all together, all at once, all in a single cycle. The front end feeds the back end. 3-issue FE means you can give the BE 3 things per cycle. 5-issue BE means you can crunch 5 things from the FE per cycle. FE = branch prediction, decode, instruction cache BE = schedule, execute, load/store, data cache
- stephencanon 12y ago
  I'm 99.9% sure that DannyBee understands this, because he's a smart guy, and that he's saying "that's how it works in marketing".
  - sliverstorm 12y ago
    I don't know DannyBee to know his smarts- but I do see the potential sarcastic undertone :) I'll leave my comment though for the edification of others.
- ChuckMcM 12y ago
  The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. So can you get the EU to the point where the all 5 of the BE units are subscribed and the three instructions in the front end have been pre-cracked waiting for a BE slot to free up? So ... Ins 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ... FE: [ ] [ ] [Ins0] BE: [ ] [ ] [ ] [ ] [ ] FE: [ ] [ ] [Ins1] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [ ] [Ins1] [Ins2] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [Ins1] [Ins5] [Ins6] BE: [ ] [Ins3] [Ins4] [Ins2] [Ins0] FE: [Ins1] [Ins5] [Ins7] BE: [Ins6] [Ins3] [Ins4] [Ins2] [Ins0] And then maybe zero retires, that lets Ins1 proceed and it retires 1, 2, 3, 4, which lets 5 proceed, that lets 6 retire and then 7 proceeds. But until I get a closer look at the TRM this is all speculation.
  - sliverstorm 12y ago
    The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. Almost certainly yes. It's supposed to be fully out-of-order, which means it should have a fully functional scheduler in between the FE & BE. Not to mention, given modern memory latencies (vs. clock speed), letting the FE run ahead is important for performance.
rayiner 12y ago
HN really does hate jokes.
brigade 12y ago
Well there's confusion over issue vs decode, dispatch, and retirement; its both accurate to say A72 is 8-wide issue and also that the relevant number is 3-wide or maybe 5-wide if you believe ARM's numbers with uop fusion. After all, the Cortex-A15 and A57 are also 8-wide issue. Incidentally all 3 are also 3-wide decode and dispatch, but A72 apparently decodes instructions to fewer uops.

sliverstorm 12y ago

8-issue means you can issue 8 things all together, all at once, all in a single cycle. The front end feeds the back end. 3-issue FE means you can give the BE 3 things per cycle. 5-issue BE means you can crunch 5 things from the FE per cycle. FE = branch prediction, decode, instruction cache BE = schedule, execute, load/store, data cache

stephencanon 12y ago
I'm 99.9% sure that DannyBee understands this, because he's a smart guy, and that he's saying "that's how it works in marketing".
- sliverstorm 12y ago
  I don't know DannyBee to know his smarts- but I do see the potential sarcastic undertone :) I'll leave my comment though for the edification of others.
ChuckMcM 12y ago
The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. So can you get the EU to the point where the all 5 of the BE units are subscribed and the three instructions in the front end have been pre-cracked waiting for a BE slot to free up? So ... Ins 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ... FE: [ ] [ ] [Ins0] BE: [ ] [ ] [ ] [ ] [ ] FE: [ ] [ ] [Ins1] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [ ] [Ins1] [Ins2] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [Ins1] [Ins5] [Ins6] BE: [ ] [Ins3] [Ins4] [Ins2] [Ins0] FE: [Ins1] [Ins5] [Ins7] BE: [Ins6] [Ins3] [Ins4] [Ins2] [Ins0] And then maybe zero retires, that lets Ins1 proceed and it retires 1, 2, 3, 4, which lets 5 proceed, that lets 6 retire and then 7 proceeds. But until I get a closer look at the TRM this is all speculation.
- sliverstorm 12y ago
  The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. Almost certainly yes. It's supposed to be fully out-of-order, which means it should have a fully functional scheduler in between the FE & BE. Not to mention, given modern memory latencies (vs. clock speed), letting the FE run ahead is important for performance.

rayiner 12y ago

HN really does hate jokes.

brigade 12y ago

Well there's confusion over issue vs decode, dispatch, and retirement; its both accurate to say A72 is 8-wide issue and also that the relevant number is 3-wide or maybe 5-wide if you believe ARM's numbers with uop fusion. After all, the Cortex-A15 and A57 are also 8-wide issue. Incidentally all 3 are also 3-wide decode and dispatch, but A72 apparently decodes instructions to fewer uops.