5 ms·

"In more detailed terms, the Cortex A72 CPU pairs a three-wide, in-order front end with a five-wide, out-of-order back end (i.e. 8-issue)." ... That's not how

"In more detailed terms, the Cortex A72 CPU pairs a three-wide, in-order front end with a five-wide, out-of-order back end (i.e. 8-issue)." ... That's not how it works. You don't add front-end and back-end width to get issue width. I know that Ars' architectural chops took a hit when Stokes left, but this is ridiculous. You take the minimum of the two[1], except that (per AnandTech's far better article [2]) the decoder is actually three fused macro-ops wide, not instructions, so the truth is actually somewhere between three and five instructions wide, depending on workload. [1] or maybe just the back-end width, since most modern CPUs can short-circuit decode in tight loops. [2] http://www.anandtech.com/show/9184/arm-reveals-cortex-a72-architecture-details http://www.anandtech.com/show/9184/arm-reveals-cortex-a72-ar...

DannyBee 12y ago
I don't think you understand how this works at all. It's like when you add a few cortex m0's to your phone, and now you have a quad-core phone. (It's 8 issue. You can issue 8 instructions to it, it just doesn't process them all in a single cycle :P)
- sliverstorm 12y ago
  8-issue means you can issue 8 things all together, all at once, all in a single cycle. The front end feeds the back end. 3-issue FE means you can give the BE 3 things per cycle. 5-issue BE means you can crunch 5 things from the FE per cycle. FE = branch prediction, decode, instruction cache BE = schedule, execute, load/store, data cache
  - stephencanon 12y ago
    I'm 99.9% sure that DannyBee understands this, because he's a smart guy, and that he's saying "that's how it works in marketing".
    - sliverstorm 12y ago
      I don't know DannyBee to know his smarts- but I do see the potential sarcastic undertone :) I'll leave my comment though for the edification of others.
  - ChuckMcM 12y ago
    The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. So can you get the EU to the point where the all 5 of the BE units are subscribed and the three instructions in the front end have been pre-cracked waiting for a BE slot to free up? So ... Ins 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ... FE: [ ] [ ] [Ins0] BE: [ ] [ ] [ ] [ ] [ ] FE: [ ] [ ] [Ins1] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [ ] [Ins1] [Ins2] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [Ins1] [Ins5] [Ins6] BE: [ ] [Ins3] [Ins4] [Ins2] [Ins0] FE: [Ins1] [Ins5] [Ins7] BE: [Ins6] [Ins3] [Ins4] [Ins2] [Ins0] And then maybe zero retires, that lets Ins1 proceed and it retires 1, 2, 3, 4, which lets 5 proceed, that lets 6 retire and then 7 proceeds. But until I get a closer look at the TRM this is all speculation.
    - sliverstorm 12y ago
      The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. Almost certainly yes. It's supposed to be fully out-of-order, which means it should have a fully functional scheduler in between the FE & BE. Not to mention, given modern memory latencies (vs. clock speed), letting the FE run ahead is important for performance.
- rayiner 12y ago
  HN really does hate jokes.
- brigade 12y ago
  Well there's confusion over issue vs decode, dispatch, and retirement; its both accurate to say A72 is 8-wide issue and also that the relevant number is 3-wide or maybe 5-wide if you believe ARM's numbers with uop fusion. After all, the Cortex-A15 and A57 are also 8-wide issue. Incidentally all 3 are also 3-wide decode and dispatch, but A72 apparently decodes instructions to fewer uops.
ajross 12y ago
I don't think note #1 is true for this core. Intel CPUs have had a micro-op cache only since Sandy Bridge. I don't think ARM is doing that yet; certainly this article doesn't hint that they are.
- stephencanon 12y ago
  The µop cache was new in Sandy Bridge, but earlier Intel and AMD micro-architectures had a loop buffer that served decoded macro-ops for tight loops, bypassing fetch and decode (in earlier designs still, it only bypassed fetch). IIRC ARM added a 32-entry loop buffer with Cortex-A15. Not sure about later designs.
ChuckMcM 12y ago
I've not looked at the actual micro-architecture yet (has ARM put it up on their site yet he wonders ... ohh goody something is up (http://infocenter.arm.com/help/topic/com.arm.doc.100095_0001_02_en/cortex_a72_mpcore_trm_100095_0001_02_en.pdf http://infocenter.arm.com/help/topic/com.arm.doc.100095_0001...) but when I read that I figured the 3 wide front end could ingest instructions until the 5 wide out of order back end was full (caveat pipeline bubbles from dependencies). That should boost the IPC of the A72 relative to the A57. I'll have to spend a couple of train trips reading the TRM to figure out if we could expect double the IPC on a typical workload.
- stephencanon 12y ago
  Looking at a few slides and reading comments on the Ars article, I think the error here is Ars' use of "i.e.". The part probably is 8 (micro-op) issue at execute, with 3 (fused macro-op) wide decode and 5 wide retire. So the "8-issue" claim could be accurate, but the way Ars presents it is just totally clueless.

DannyBee 12y ago

I don't think you understand how this works at all. It's like when you add a few cortex m0's to your phone, and now you have a quad-core phone. (It's 8 issue. You can issue 8 instructions to it, it just doesn't process them all in a single cycle :P)

sliverstorm 12y ago
8-issue means you can issue 8 things all together, all at once, all in a single cycle. The front end feeds the back end. 3-issue FE means you can give the BE 3 things per cycle. 5-issue BE means you can crunch 5 things from the FE per cycle. FE = branch prediction, decode, instruction cache BE = schedule, execute, load/store, data cache
- stephencanon 12y ago
  I'm 99.9% sure that DannyBee understands this, because he's a smart guy, and that he's saying "that's how it works in marketing".
  - sliverstorm 12y ago
    I don't know DannyBee to know his smarts- but I do see the potential sarcastic undertone :) I'll leave my comment though for the edification of others.
- ChuckMcM 12y ago
  The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. So can you get the EU to the point where the all 5 of the BE units are subscribed and the three instructions in the front end have been pre-cracked waiting for a BE slot to free up? So ... Ins 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ... FE: [ ] [ ] [Ins0] BE: [ ] [ ] [ ] [ ] [ ] FE: [ ] [ ] [Ins1] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [ ] [Ins1] [Ins2] BE: [ ] [ ] [ ] [ ] [Ins0] FE: [Ins1] [Ins5] [Ins6] BE: [ ] [Ins3] [Ins4] [Ins2] [Ins0] FE: [Ins1] [Ins5] [Ins7] BE: [Ins6] [Ins3] [Ins4] [Ins2] [Ins0] And then maybe zero retires, that lets Ins1 proceed and it retires 1, 2, 3, 4, which lets 5 proceed, that lets 6 retire and then 7 proceeds. But until I get a closer look at the TRM this is all speculation.
  - sliverstorm 12y ago
    The question for me is whether you can retire the FE issue with a BE dispatch, and if so pull in another FE issue. Almost certainly yes. It's supposed to be fully out-of-order, which means it should have a fully functional scheduler in between the FE & BE. Not to mention, given modern memory latencies (vs. clock speed), letting the FE run ahead is important for performance.
rayiner 12y ago
HN really does hate jokes.
brigade 12y ago
Well there's confusion over issue vs decode, dispatch, and retirement; its both accurate to say A72 is 8-wide issue and also that the relevant number is 3-wide or maybe 5-wide if you believe ARM's numbers with uop fusion. After all, the Cortex-A15 and A57 are also 8-wide issue. Incidentally all 3 are also 3-wide decode and dispatch, but A72 apparently decodes instructions to fewer uops.

ajross 12y ago

I don't think note #1 is true for this core. Intel CPUs have had a micro-op cache only since Sandy Bridge. I don't think ARM is doing that yet; certainly this article doesn't hint that they are.

stephencanon 12y ago
The µop cache was new in Sandy Bridge, but earlier Intel and AMD micro-architectures had a loop buffer that served decoded macro-ops for tight loops, bypassing fetch and decode (in earlier designs still, it only bypassed fetch). IIRC ARM added a 32-entry loop buffer with Cortex-A15. Not sure about later designs.

ChuckMcM 12y ago

I've not looked at the actual micro-architecture yet (has ARM put it up on their site yet he wonders ... ohh goody something is up (http://infocenter.arm.com/help/topic/com.arm.doc.100095_0001_02_en/cortex_a72_mpcore_trm_100095_0001_02_en.pdf http://infocenter.arm.com/help/topic/com.arm.doc.100095_0001...) but when I read that I figured the 3 wide front end could ingest instructions until the 5 wide out of order back end was full (caveat pipeline bubbles from dependencies). That should boost the IPC of the A72 relative to the A57. I'll have to spend a couple of train trips reading the TRM to figure out if we could expect double the IPC on a typical workload.

stephencanon 12y ago
Looking at a few slides and reading comments on the Ars article, I think the error here is Ars' use of "i.e.". The part probably is 8 (micro-op) issue at execute, with 3 (fused macro-op) wide decode and 5 wide retire. So the "8-issue" claim could be accurate, but the way Ars presents it is just totally clueless.