2 ms·
Try to start modeling your problem as a state machine. Separate the combinational and the sequential part in two state machines. The flow becomes quite similar
by aprdm 12y ago
Try to start modeling your problem as a state machine.
Separate the combinational and the sequential part in two state machines.
The flow becomes quite similar to regular embedded system software (that can be programmed using state machine pattern as well).
Say
e.g:
state read_input =>
reg_a <= input
next_state <= multiply_input_by_10
state multiply_input_by_10 =>
reg_b <= reg_a * 10
next_state <= finish
state send_to_output =>
finish_reg <= '1'
and then parallel to that you would have
finish_wire <= finish_reg
value_wire <= reg_b
or something like that, sorry for the bad example but definitely use state machines
- platz 12y agoSounds like flow-based-programming or even FRP (e.g. netwire)
- alain94040 12y agoI started writing a (hopefully) better and clearer tutorial of what is HDL for programmers. Feel free to contribute at https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for_Software_Programmers https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...