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This is really cool. The article is pretty light on the technical details about the actual processor architecture. I think their choice of naming is unfortuna
by unwind 12y ago
This is really cool.
The article is pretty light on the technical details about the actual processor architecture.
I think their choice of naming is unfortunate, confusion with ARM's Cortex-M3 is quite likely. Or are you supposed to pronounce this "M to the third" or something?
Update: D'oh, of course it's "M-cubed". I knew that, I blame not being a native speaker for not thinking about it. :)
- Quanticles 12y agoThey usually pronounce it "M-cubed", which is also unfortunate because the university started some sort of research program (also called "M-cubed") a while after that name got engrained
- rhinoceraptor 12y agoIt probably doesn't help that Ann Arbor is called A^2.
- giodamelio 12y agoI would go with "M cubed"
- saticmotion 12y agoI think you might be able to find more details on Blaauw's website[0]. I've also found a page with their publications[1] [0]http://blaauw.eecs.umich.edu/project.php http://blaauw.eecs.umich.edu/project.php [1]http://blaauw.eecs.umich.edu/resource.php?grp=1 http://blaauw.eecs.umich.edu/resource.php?grp=1
- walterbell 12y agoFrom that list, a 2013 overview of the platform (pdf): http://blaauw.eecs.umich.edu/getFile.php?id=498 http://blaauw.eecs.umich.edu/getFile.php?id=498 AnnArbor SmartZone funding, http://www.a2gov.org/departments/finance-admin-services/smart-zone/Pages/Home.aspx http://www.a2gov.org/departments/finance-admin-services/smar... U of M test track for smart/autonomous cars, http://www.mlive.com/news/ann-arbor/index.ssf/2014/03/university_of_michigan_approve_3.html http://www.mlive.com/news/ann-arbor/index.ssf/2014/03/univer...
- 13 12y agoI didn't even consider that this might not be ARM. There's Cortex M0, M1, M3, M4 you'd be silly to call a product M^3 if it wasn't related. If not it would be lawsuit fodder because it certainly sounds too related to be coincidental.
- xgbi 12y agoProcessor description is here: http://www.ee.columbia.edu/~mgseok/pdfs/phoenix_isscc_dac_design_contest.pdf http://www.ee.columbia.edu/~mgseok/pdfs/phoenix_isscc_dac_de... I'm not sure it's an ARM..
- unwind 12y agoThanks! No, it's definitely not ARM, that was my point. It seems to consist of "8-bit CPU, a 52x40-bit DMEM, a 64x10-bit IMEM, a 64x10-bit IROM". Those are some seriously small memory sizes, a total of 64 instructions (the IROM holds the code) really isn't a lot to play with.
- ansible 12y agoYes. Though if the silicon process technology is as good as they claim, then scaling that up a little bit (to be on-par with conventional 8-bit micros) won't be too bad. It will be interesting to see if they can maintain the kind of leakage they're talking about with a smaller process size.