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That is exactly what make supports out of the box. If ${CC} is missing from the Makefile, ${CC} is globally set to the system C compiler i.e. cc Users can use
by tobik 12y ago
That is exactly what make supports out of the box. If ${CC} is missing from the Makefile, ${CC} is globally set to the system C compiler i.e. cc
Users can use a different compiler by specifying it on the command line via e.g.
make CC=clang
Some people set
CC=gcc
in their Makefile to force the usage of gcc. Never do this. Do this instead:
CC?=gcc
That way users can still override the value of ${CC} on the command line if they want to.
- dietrichepp 12y ago> CC?=gcc This is only relevant if you want portability to other versions of Make. I simply don't care about anybody who's not using GNU Make these days. Try it yourself: command line options override variables in makefiles unless "override" is specified for that assignment.