In the old 3-stage ARM pipeline, the instruction reads pc (as with all registers) during the execute stage, which is 2 cycles after fetch. ARM froze this defini

In the old 3-stage ARM pipeline, the instruction reads pc (as with all registers) during the execute stage, which is 2 cycles after fetch. ARM froze this definition for compatibility, so it's +8 for ARM and +4 for thumb despite not using a 3-stage pipeline anymore.