You make a very good point. I do like to give you one additional aspect to consider: While the Mill saves on instruction scheduling logic (and register renaming

You make a very good point. I do like to give you one additional aspect to consider: While the Mill saves on instruction scheduling logic (and register renaming, and certainly also has the benefit of re-thinking opcodes and instruction decode), there are other features that add complexity again. Making a subroutine call appear as if it were a single instruction has got to be tricky, for example. In the end, I have only seen CPU design from a physical design tool support point of view. I don't really have the necessary experience to judge the relative complexity of out-of-order+register renaming vs. whatever the Mill aims to do. You're probably right that the Mill is simpler. Part of it is that all we really know about all this comes from a bunch of talks that focus on what the Mill looks like to the user. Who knows what their physical design story is. I just hope, for their own sake, that they have been working on that part of it for a significant amount of time as well.