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Hi, I understand and agree with what you say and like the functional language suggestion perhaps augmented as in functional-reactive (a hunch), but I can't help

Hi, I understand and agree with what you say and like the functional language suggestion perhaps augmented as in functional-reactive (a hunch), but I can't help pointing at a post from the Xilinx blog yesterday praising a workflow that leaves out HDL in favour of C++, so the world is getting more complex. "Now, although you don’t see any Verilog or VHDL in the above tool flow,..." http://forums.xilinx.com/t5/Xcell-Daily-Blog/SDSoC-development-environment-for-Zynq-SoCs-MPSoCs-says-buh-bye/ba-p/568862 http://forums.xilinx.com/t5/Xcell-Daily-Blog/SDSoC-developme... Though Zynq is ARM+FPGA, in principle one should be able to do the same with a soft processor cum custom coprocessing logic in a fpga-only thing.

rthomas6 12y ago
That's really cool. It looks like the ARM is doing the heavy lifting, though, and is supplemented by custom hardware (likely Xilinx's many hardware IPs) that the ARM farms things out to. I'm not saying this sort of thing has no place, and I think it's awesome, but you need the ASIC processor for this to be fast. This is perfect for Zynq because of the built-in ARM. You are right that it is also possible with just an FPGA, but FPGA logic is an order of magnitude slower than ASIC. People still do this sort of thing with soft processors though. Probably a lot. The limits of this is you're not making custom IP, but rather using a library of digital logic designs provided by Xilinx. Which works well for a lot of use cases, but it's not on the same abstraction level as actually describing the hardware itself.
- jesuslop 12y ago
  Well said.