Register machines have no particular problems with cache due to random access. The typical arrangement is that there are instructions that allocate and dealloca

Register machines have no particular problems with cache due to random access. The typical arrangement is that there are instructions that allocate and deallocate a block of N contiguous slots from a stack, and "registers" refer to storage within the currently allocated block. This isn't any worse than a stack machine. There is a real issue with instruction density, however, in that the interpreter will touch many cache lines containing instructions in an unpredictable order. An inefficient encoding will result in overhead due to cache lines being taken away from program data to serve the interpreter.