3 ms·

I'm not an expert on interpreters, but from the description it sounds like register machines are very CPU cache unfriendly, whereas stacks by their nature are v

I'm not an expert on interpreters, but from the description it sounds like register machines are very CPU cache unfriendly, whereas stacks by their nature are very cache friendly by their nature. (It's a complicated subject, but the basic idea is: contiguous memory is cache friendly, random access is not). Given how catastrophic cache misses can be for performance (LOTS of CPU stalling), I imagine the instruction density really doesn't mean much compared to keeping the CPU fed with instructions. The part of all this that is hard is that, when you're working at this abstraction level, you're not writing for an abstract machine, you're writing for real computers that are highly pipelined and heavily dependent on relatively small caches.

gsg 12y ago
Register machines have no particular problems with cache due to random access. The typical arrangement is that there are instructions that allocate and deallocate a block of N contiguous slots from a stack, and "registers" refer to storage within the currently allocated block. This isn't any worse than a stack machine. There is a real issue with instruction density, however, in that the interpreter will touch many cache lines containing instructions in an unpredictable order. An inefficient encoding will result in overhead due to cache lines being taken away from program data to serve the interpreter.