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An ex manager from DARPA, which was responsible for similar stuff there said he believes that 5nm is the physical limit of scaling. but making them will be more

by minthd 12y ago

An ex manager from DARPA, which was responsible for similar stuff there said he believes that 5nm is the physical limit of scaling. but making them will be more complex, hence expensive, and he think the economics could stop working before. Also if we're talking about the economics, there really are 2 foundries(TSMC and Globalfounries/Samsung alliance) make top-end chip for others(Intel doesn't count, chip designers don't/won't trust them). Do with almost no competition - do you expect prices to go down ? So maybe we will see further performance improvements, But no cost reductions.

ethbro 12y ago
> So maybe we will see further performance improvements, But no cost reductions. Don't mean to be snarky, but how can the industry see performance improvements without cost reductions? Assuming new process technology produces chips with equivalent performance to current models at the same cost (aka $/mm2 increases in step with performance), but allows more thermal headroom for higher performance models than current models (at additional cost), then wouldn't that be economically infeasible? I can't imagine with massively-parallel-on-commodity-hardware for datacenter processing (correct/incorrect characterization?) there's enough aggregate demand for "more performance at higher total cost" to subsidize an entirely new process node...
- minthd 12y ago
  >> but how can the industry see performance improvements without cost reductions? I imagine for example, data centers willing to pay the same price for a chip that only reduces power. Or that chips that will be twice as fast but cost double, but they'll allow to double the density in the server room, etc. BTW that's what already happening in mobile SOC - the new process nodes aren't cheaper, only lower in power.
  - ethbro 12y ago
    > I imagine for example, data centers willing to pay the same price for a chip that only reduces power. That's not valid with the original statement though. Unless the new chip that costs the same but runs at reduced power does not have an lower-cost version that runs at the previous power. Not seeing the logic here. If a mobile SoC of performance X and TDP Y and cost Z on the previous node, and the current node provides performance X at TDP<Y and cost Z on the current node, then you could substitute a lower performance part, running at the previous node's power envelope, and realize cost savings (e.g. performance X(OC <X -> X) at TDP Y(OC <Y -> Y) at cost <Z). I'm not seeing the possibility of "performance improvements without cost reductions" other than at the ultra-high-end (aka "what was previously not possible").

by minthd 12y ago

ethbro 12y ago

> So maybe we will see further performance improvements, But no cost reductions. Don't mean to be snarky, but how can the industry see performance improvements without cost reductions? Assuming new process technology produces chips with equivalent performance to current models at the same cost (aka $/mm2 increases in step with performance), but allows more thermal headroom for higher performance models than current models (at additional cost), then wouldn't that be economically infeasible? I can't imagine with massively-parallel-on-commodity-hardware for datacenter processing (correct/incorrect characterization?) there's enough aggregate demand for "more performance at higher total cost" to subsidize an entirely new process node...

minthd 12y ago
>> but how can the industry see performance improvements without cost reductions? I imagine for example, data centers willing to pay the same price for a chip that only reduces power. Or that chips that will be twice as fast but cost double, but they'll allow to double the density in the server room, etc. BTW that's what already happening in mobile SOC - the new process nodes aren't cheaper, only lower in power.
- ethbro 12y ago
  > I imagine for example, data centers willing to pay the same price for a chip that only reduces power. That's not valid with the original statement though. Unless the new chip that costs the same but runs at reduced power does not have an lower-cost version that runs at the previous power. Not seeing the logic here. If a mobile SoC of performance X and TDP Y and cost Z on the previous node, and the current node provides performance X at TDP<Y and cost Z on the current node, then you could substitute a lower performance part, running at the previous node's power envelope, and realize cost savings (e.g. performance X(OC <X -> X) at TDP Y(OC <Y -> Y) at cost <Z). I'm not seeing the possibility of "performance improvements without cost reductions" other than at the ultra-high-end (aka "what was previously not possible").