4 ms·

This reminds me of something I'm curious about: why have L1 caches have been the same size for quite a few generations of Intel Core processors?

vardump 12y ago
Currently Intel's L1D (level 1 data) cache is 512 lines with 64 bytes each, 32 kB. Been that way for a pretty long time. L1D latency with a pointer is mostly 4 cycles. Not sure, but I think having 1024 entries would increase that to 5 cycles. Increasing cache line size from 64 bytes to 128 bytes would require more memory (DDRx SDRAM) bandwidth, because CPU needs to always fill a whole 64 byte - 128 byte with this change - cache line on a memory load. Even if you want just one byte. Wasted bandwidth for non-streaming workloads would be increased significantly. This change would force also L2 to have 128 byte cache lines, etc. LFBs and other buffers would of course also need to accommodate this. Skylake will be able to process 64 bytes (512 bits) with a single SIMD instruction, with AVX-512. Perhaps Intel will need to soon increase cache line size, if 1024 bits wide SIMD instructions are desired. SIMD gather instructions might be a hint that in the future memory loads will function in a different fashion. Maybe cache lines won't anymore be the smallest amount of data a CPU memory subsystem can deal with?
wmf 12y ago
Because that size is optimal, regardless of transistor size. Making the cache larger makes it slower (because of the speed of light AFAIK) and more power-hungry which reduces overall performance.
jjoonathan 12y ago
This reminds me of something I'm curious about: why aren't large SRAM arrays displaying DRAM? I know 6Ts are larger than 1T+1C, but even if SRAM were 6x as expensive (which ought to be a severe upper bound) that would put it at $50/GB which sounds like it could easily be worthwhile for certain workloads -- not unlike SSDs a few years ago. The latency advantage would be gigantic, especially if you could crowd the chips near the CPU. Is SRAM comparatively power hungry or something?
- vardump 12y ago
  I think SRAM cost is more like $1500/GB.
  - jjoonathan 12y ago
    Are you familiar with an immensely super-linear cost scaling in the # of transistors vs DRAM or are you quoting a cost figure for putting SRAM on the CPU die? If you put DRAM on the CPU die I would also expect it to cost hundreds per GB, but that's not a very interesting comparison because we know from current DRAM best practices that you can put it on its own die at a much lower cost.
- wmf 12y ago
  RLDRAM exists, so SRAM would have to beat that. In your 6x upper bound maybe you're not taking into account (dis)economies of scale that could cause SRAM to be much more expensive.
  - jjoonathan 12y ago
    What diseconomies of scale do you mean? If you mean that demand is low right now and so there is no economy of scale yet, that's hardly evidence against a gradual market takeover. That's what investors and early adopters are for, see: SSDs. If you really do mean diseconomy of scale, where unit price will rise with the number of units produced, what would produce such an effect in the SRAM market? Chip fab is almost always in the opposite regime, what's so unique about SRAM? Also, I looked up RLDRAM [1] and it looks like their "low" latencies are still 10ns, which is good for DRAM but abysmal in comparison to SRAM. [1] http://www.micron.com/products/dram/rldram-memory/1_15Gb#/ http://www.micron.com/products/dram/rldram-memory/1_15Gb#/

vardump 12y ago

Currently Intel's L1D (level 1 data) cache is 512 lines with 64 bytes each, 32 kB. Been that way for a pretty long time. L1D latency with a pointer is mostly 4 cycles. Not sure, but I think having 1024 entries would increase that to 5 cycles. Increasing cache line size from 64 bytes to 128 bytes would require more memory (DDRx SDRAM) bandwidth, because CPU needs to always fill a whole 64 byte - 128 byte with this change - cache line on a memory load. Even if you want just one byte. Wasted bandwidth for non-streaming workloads would be increased significantly. This change would force also L2 to have 128 byte cache lines, etc. LFBs and other buffers would of course also need to accommodate this. Skylake will be able to process 64 bytes (512 bits) with a single SIMD instruction, with AVX-512. Perhaps Intel will need to soon increase cache line size, if 1024 bits wide SIMD instructions are desired. SIMD gather instructions might be a hint that in the future memory loads will function in a different fashion. Maybe cache lines won't anymore be the smallest amount of data a CPU memory subsystem can deal with?

wmf 12y ago

Because that size is optimal, regardless of transistor size. Making the cache larger makes it slower (because of the speed of light AFAIK) and more power-hungry which reduces overall performance.

jjoonathan 12y ago

This reminds me of something I'm curious about: why aren't large SRAM arrays displaying DRAM? I know 6Ts are larger than 1T+1C, but even if SRAM were 6x as expensive (which ought to be a severe upper bound) that would put it at $50/GB which sounds like it could easily be worthwhile for certain workloads -- not unlike SSDs a few years ago. The latency advantage would be gigantic, especially if you could crowd the chips near the CPU. Is SRAM comparatively power hungry or something?

vardump 12y ago
I think SRAM cost is more like $1500/GB.
- jjoonathan 12y ago
  Are you familiar with an immensely super-linear cost scaling in the # of transistors vs DRAM or are you quoting a cost figure for putting SRAM on the CPU die? If you put DRAM on the CPU die I would also expect it to cost hundreds per GB, but that's not a very interesting comparison because we know from current DRAM best practices that you can put it on its own die at a much lower cost.
wmf 12y ago
RLDRAM exists, so SRAM would have to beat that. In your 6x upper bound maybe you're not taking into account (dis)economies of scale that could cause SRAM to be much more expensive.
- jjoonathan 12y ago
  What diseconomies of scale do you mean? If you mean that demand is low right now and so there is no economy of scale yet, that's hardly evidence against a gradual market takeover. That's what investors and early adopters are for, see: SSDs. If you really do mean diseconomy of scale, where unit price will rise with the number of units produced, what would produce such an effect in the SRAM market? Chip fab is almost always in the opposite regime, what's so unique about SRAM? Also, I looked up RLDRAM [1] and it looks like their "low" latencies are still 10ns, which is good for DRAM but abysmal in comparison to SRAM. [1] http://www.micron.com/products/dram/rldram-memory/1_15Gb#/ http://www.micron.com/products/dram/rldram-memory/1_15Gb#/