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There was hope 20 years ago, when NeoCAD wrote an independent partition-place-route tool for Xilinx chips, but then Xilinx bought them [1]. No action since the

by femto 12y ago

There was hope 20 years ago, when NeoCAD wrote an independent partition-place-route tool for Xilinx chips, but then Xilinx bought them [1]. No action since then. I've thought about this over the last 20 years. In my opinion, designing a free FPGA from scratch and writing the requisite tools would have to be be a serious option for someone considering taking on the task of reverse engineering and tracking the development of existing FPGAs. It probably wouldn't be much more work for a person with the requisite knowledge and the result would be "more free", by not having to follow the silicon manufacturer's elephant. Then again, buying an FPGA and spending a heap of time reverse engineering it is more accessible to the average hacker than designing and building an FPGA chip. [1] http://www.xilinx.com/publications/archives/xcell/Xcell17.pdf http://www.xilinx.com/publications/archives/xcell/Xcell17.pd... --- Edit: Delete unused reference

krupan 12y ago
At this point I'd be happy with just a Free multi-language simulator, let alone synthesis tools. There are a couple Free verilog-only or vhdl-only ones, but any modern project, for better or worse, has a combination of verilog, SystemVerilog, vhdl, and probably some verification-language testbench stuff (specman/vera). Also, the current free simulators don't have the advantages that gcc had over commercial compilers mentioned. They are slower, have worse error messages (hard to believe that's possible but it really is), and worse language support. So sad.
- keenerd 12y ago
  Writing GPL'd synthesis stuff is the #1 item on my "things to do when independently wealthy" list. Personally I'd start with reverse engineering Lattice's FPGAs. They have the most documentation and the simplest chips. Plus as the third horse in the FPGA business they might be the most amiable about the advantages being more open provide.

by femto 12y ago

krupan 12y ago

At this point I'd be happy with just a Free multi-language simulator, let alone synthesis tools. There are a couple Free verilog-only or vhdl-only ones, but any modern project, for better or worse, has a combination of verilog, SystemVerilog, vhdl, and probably some verification-language testbench stuff (specman/vera). Also, the current free simulators don't have the advantages that gcc had over commercial compilers mentioned. They are slower, have worse error messages (hard to believe that's possible but it really is), and worse language support. So sad.

keenerd 12y ago
Writing GPL'd synthesis stuff is the #1 item on my "things to do when independently wealthy" list. Personally I'd start with reverse engineering Lattice's FPGAs. They have the most documentation and the simplest chips. Plus as the third horse in the FPGA business they might be the most amiable about the advantages being more open provide.