For a less complete approach, look at what how the lowRISC project has proposed to extend the RISC-V architecture with a couple of tag bits: http://www.lowrisc.

For a less complete approach, look at what how the lowRISC project has proposed to extend the RISC-V architecture with a couple of tag bits: http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-minion-cores/ http://www.lowrisc.org/docs/memo-2014-001-tagged-memory-and-...