4 ms·
Yep, it's got 32 GPRs, with #0 hardwired to the constant 0. And the lowRISC project is looking into adding two tag bits with a focus on practical security for
by hga 12y ago
Yep, it's got 32 GPRs, with #0 hardwired to the constant 0.
And the lowRISC project is looking into adding two tag bits with a focus on practical security for languages like C, but with the ability to use them for things like GC.
Largest nits I see about the RISC-V ISA is no support for integer math error checking aside from divide by zero (a New Jersey design), and per a slide set I found for the January workshop, the work in progress 64 bit VMM mode will only support 43 bits of address space, i.e. "only" 8 TiB, vs. e.g. the 256 TiB of x86-64. Which of course is rather a lot, but I find it uncomfortably close to the DRAM you can put on current systems with Intel CPUs; I've watched this game way too many time in my career.
- aidenn0 12y agoThe 43-bits; is that a limitation on physical or virtual addresses? Also, don't forget that DRAM isn't the only consumer of physical address space.
- hga 12y agoIt's from a slide set, the first draft of RISC-V's "Privileged ISA Specification" is still being worked on before initial release, which is supposed to happen RSN. I'm assuming it's the virtual address space limit.