A current generation Hawsell chip can easily manage terabytes per second in on-chip cache and by manipulating registers. Eight or more virtual cores plus SIMD

A current generation Hawsell chip can easily manage terabytes per second in on-chip cache and by manipulating registers. Eight or more virtual cores plus SIMD operations that can smash against large chunks of data per cycle adds up awfully fast on a 4GHz chip. They're also probably counting the fact that data flows from one system to another in sequence, but adding up each sequence. Eight streams of 150 gigabytes per second for example. This doesn't count information that's captured but discarded at the source, processed away before it's transmitted downstream.