4 ms·

The VHDL defines a reset and reset conditions, actually uses a clock, and many other things that the Cx code is leaving out.

• MootWoop 12y ago
  Exactly! Isn't that a breeze? Reset and clock are implicit by default, but you can always override them (change name, set reset synchronous, etc.)
  • kw71 12y ago
    Very cool, I was wondering where the clock was.