4 ms·
The authors point still holds if writes might not appear in program order on other CPU sockets, not just other cores within the same socket. Do you have a refe
by martincmartin 12y ago
The authors point still holds if writes might not appear in program order on other CPU sockets, not just other cores within the same socket.
Do you have a reference for the strong memory ordering on x86? I'd like to read more about it.
- rayiner 12y agox86 enforces (essentially) total store order across all sockets: http://www.cl.cam.ac.uk/~pes20/weakmemory/index3.html http://www.cl.cam.ac.uk/~pes20/weakmemory/index3.html. The barriers are still useful for kernel code because other processors on the machine usually don't participate in the cache-coherency protocol.