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In some ways this modern hybrid is better than either. RISC CPUs were almost always internally more efficient due to the simpler decode and easier application o
by voidlogic 12y ago
In some ways this modern hybrid is better than either. RISC CPUs were almost always internally more efficient due to the simpler decode and easier application of performance tricks; whereas CISC was always better externally as it had better memory/instruction density. So in some ways the CISC on the outside, RISC in the inside approach is the best thing that could have happened for a CISC arch. like x86.
- 1amzave 12y ago> CISC was always better externally ...aside from being orders of magnitude more of an ass-pain if you ever have to write software that actually deals with machine code (at least on x86; perhaps other CISCs aren't as bad). Simple example: given an instruction boundary, find the preceding instruction boundary. On most any RISC it's trivial (subtract 4, or perhaps 2 in some cases). On x86...I'm not an expert, but I'm about 80% confident it's basically impossible to do in the general case.
- voidlogic 12y ago>...aside from being orders of magnitude more of an ass-pain if you ever have to write software that actually deals with machine code 1. I was talking about external as in the memory hierarchy not development effort. >(at least on x86; perhaps other CISCs aren't as bad). This, the PDP-11 machines have a lovely instruction set for example.
- Ded7xSEoPKYNsDd 12y agoThis is certainly impossible on x86 - you can even interleave two different instruction streams (which is mainly used to confuse static analysis tools).