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Remember, within a generation these chips are almost all made from the same set of masks. None of these disabled features save any transistors or die area I th

by nkurz 12y ago

Remember, within a generation these chips are almost all made from the same set of masks. None of these disabled features save any transistors or die area I think it might be true for CPUID/stepping, but not for what are usually considered to be the generations. For example, there look to be at least 5 dies sizes for Sandy Bridge: http://en.wikipedia.org/wiki/Sandy_Bridge#Models_and_steppings http://en.wikipedia.org/wiki/Sandy_Bridge#Models_and_steppin... I haven't tried to match up the supported ISA's with the different die sizes, but I presume they'd correlate. Do they not?

wtallis 12y ago
The quad-core Sandy Bridge could end up labeled as a Core i5, Core i7, or Xeon E3. The dual core Sandy Bridge could be labeled as a Pentium, Celeron, Core i3, Core i5, Core i7 (mobile), or Xeon E3. The server designs (LGA2011) have QPI links and may be the only memory controllers capable of using registered memory. But among the processors targeting the LGA1155 and mobile platforms, they only had one core design and only one memory controller design that was shared across all products though never with everything enabled at once.
- nkurz 12y ago
  Yes, I agree, number of cores and size of L3 are commonly cases cases where functionality is disabled. But do you know which of the other factors listed in the article that this is true for? For example, are there cases where two processors share the same die but one supports AVX and the other does not? I don't know the answer, but if there are not, this would substantially undercut the argument in the main article.
  - wtallis 12y ago
    Sandy Bridge and Ivy Bridge Celerons and Pentiums use the same die as the corresponding Core i3s, but only the i3 supports AVX in the CPU and QuickSync in the GPU. AES instructions aren't available on the i3 but are present on the dual-core i5. Haswell no longer discriminates with QuickSync, and extends AES down to the i3s but still not the Celerons and Pentiums. None of these features are unavailable due to being physically absent. They're just turned off. If Intel's microcode format and DRM were reverse engineered, some of the features could be turned back on.
    - nkurz 12y ago
      Thanks for the great info. That was the part I couldn't figure out from the article or the specs.
- vardump 12y ago
  Artificially disabling ECC (error correcting) SDRAM support is very disappointing. In my experience ECC significantly improves stability. Laptops (without ECC RAM) crash a few times per year, desktops with ECC RAM can run stable for years.

by nkurz 12y ago

wtallis 12y ago

The quad-core Sandy Bridge could end up labeled as a Core i5, Core i7, or Xeon E3. The dual core Sandy Bridge could be labeled as a Pentium, Celeron, Core i3, Core i5, Core i7 (mobile), or Xeon E3. The server designs (LGA2011) have QPI links and may be the only memory controllers capable of using registered memory. But among the processors targeting the LGA1155 and mobile platforms, they only had one core design and only one memory controller design that was shared across all products though never with everything enabled at once.

nkurz 12y ago
Yes, I agree, number of cores and size of L3 are commonly cases cases where functionality is disabled. But do you know which of the other factors listed in the article that this is true for? For example, are there cases where two processors share the same die but one supports AVX and the other does not? I don't know the answer, but if there are not, this would substantially undercut the argument in the main article.
- wtallis 12y ago
  Sandy Bridge and Ivy Bridge Celerons and Pentiums use the same die as the corresponding Core i3s, but only the i3 supports AVX in the CPU and QuickSync in the GPU. AES instructions aren't available on the i3 but are present on the dual-core i5. Haswell no longer discriminates with QuickSync, and extends AES down to the i3s but still not the Celerons and Pentiums. None of these features are unavailable due to being physically absent. They're just turned off. If Intel's microcode format and DRM were reverse engineered, some of the features could be turned back on.
  - nkurz 12y ago
    Thanks for the great info. That was the part I couldn't figure out from the article or the specs.
vardump 12y ago
Artificially disabling ECC (error correcting) SDRAM support is very disappointing. In my experience ECC significantly improves stability. Laptops (without ECC RAM) crash a few times per year, desktops with ECC RAM can run stable for years.