8 ms·

Sandy bridge, Ivy bridge, Haswell and the mess of Intel processors feature list

116 points by shodanshok 12y ago

billions 12y ago
Moore's law is over. Pentium 4s reached 3GHZ 15 years ago. CPUs try things like parallelizing while the human brain thinks sequentially. CPUs are still getting faster but at an incrementally slower rate. A 4 year old Macbook Air is half as performant as the latest. In previous decades, the performance gains were 2-5X per year. A paradigm shift (quantum computing?) needs to happen soon so computation can continue scaling.
- nemothekid 12y ago
  Moore's law was never about performance.
  - billions 12y ago
    Moore's law is about the number of transistors on a chip which is reaching a limit because heat cannot be dissipated fast enough. Heat is the primary limit on performance.
    - sliverstorm 12y ago
      More transistors is still better, even if they need to be off most of the time. You can spend more silicon on advanced features, just like AVX, spending transistor count for performance at neutral power cost.
- Zigurd 12y ago
  The illusion of the Cartesian theater is seemingly sequential. Your brain is not.
  - billions 12y ago
    Here's a bit more on linear thinking: http://en.wikipedia.org/wiki/Cocktail_party_effect http://en.wikipedia.org/wiki/Cocktail_party_effect *Feel free to send more insults my way if it fulfills your ego. I am here to listen, but please keep the discussion constructive for the sake of the community.
- DigitalJack 12y ago
  "In previous decades, the performance gains were 2-5X per year." What decade was that? According to this[1], it's never been better than ~50% year over year. [1] http://www.cs.columbia.edu/~sedwards/classes/2012/3827-spring/advanced-arch-2011.pdf http://www.cs.columbia.edu/~sedwards/classes/2012/3827-sprin...
hayksaakian 12y ago
I've noticed that CPU companies are focusing more and more on power efficiency to compete with ARM potentially. Maybe turning off the features described in the OP makes lower end CPUs run faster? That might be significant since i also presume most laptops use those same lower end CPUs. Laptops being the ones that need to save energy much of the time. (Desktops are obviously plugged in). This is probably most significant in the Microsoft Surface (it uses a real intel CPU if i recall correctly). I wonder which features it has marked "off" , and what impact that has on battery power.
- icegreentea 12y ago
  The "lowest" end of the CPUs that the OP discusses are low end desktop/laptop parts. Furthermore, the biggest criticism of the author isn't the feature disabling per se, but how inconsistently Intel applies it across their overall performance bins. For example, the lack of TXT support in high end i7 parts when its there for middle tier i5 parts. Why the i7-3990K has VT-d and the i7-3770K doesnt(which really should just be distinguished by their clock/cache/TDP).
  - ptysiu 12y ago
    3770K cpu has basic version 3770, which has the VT-d ext. There is no such thing like 3990k.
- wtallis 12y ago
  Remember, within a generation these chips are almost all made from the same set of masks. None of these disabled features save any transistors or die area; the disabling just leaves you with a dead spot on the chip. So the real question is if you've got the hardware in place to provide these special features, can you save any power by not using those features? The answer is that you only save power by not doing at all the things those features accelerate. It's never more efficient to implement AES through general-purpose instructions than using the fixed-function hardware. If you've got a workload that can benefit from the wider SIMD units, it won't save any energy to only use the narrower instructions. If you're trying to secure or virtualize your OS, doing it with VT-x and VT-d will be so much faster than emulating it in software that even if those features added several watts to the chips power consumption you would still save energy. Doing less can save power, but doing the same amount of stuff the hard way doesn't help anything.
ChuckMcM 12y ago
The author makes a point, when CPUs are "good enough" its a real problem for CPU manufacturers. They don't price them to have a service life of 15 years, they expect them to be replaced every 2 - 3 years. And the option there is to featurize them. It is interesting to watch in the ARM space as well.
nkurz 12y ago
As someone excited by the improvements that are possible moving from AVX to AVX2, I was recently surprised to learn that Intel has chips released this year that do not support AVX. AVX-512 is still supposedly scheduled for release next year with Skylake. How long do you suppose until it's reasonable to presume that most processors will support it? SSE 4.2 came out in 2008 and appears to be the baseline now, so 5 years seems like a reasonable guess. It's hard to believe this degree of ISA segmentation is going to benefit Intel in the end.
- wtallis 12y ago
  I think that the SIMD instructions are well past the point of diminishing returns, both for the kinds of instructions provided and the width of the vectors. I'm more interested in how VT-d and TSX allow different software architectures, if and only if you can design your OS around the assumption that they're available. By only including them on select models, Intel's making them much less useful even for the customers who want to pay extra to have those features.
  - thechao 12y ago
    I used to write software rasterizers in a past life. AVX-512 is straight-up an observed 8x performance gain over SSE: a well-written software rasterizer is a very clever thread-scheduling algorithm wrapped around long lists of FMA-load/store sequences. I know that ray-tracers, databases, and other 'big data' all gain equally-well from AVX-512. The IO-request depth on these new parts is such that, for ALU-heavy work, with good IO-spread, memory latency is completely hidden---fetch time is still ~250-300c, but you just no longer see it. The only thing I miss is 'addsets', which was dropped from LRBni, as this instruction was 'the rasterizer function': it now requires a fairly involved sequence to replicate in AVX-512. Pining for other lost things: if we had the LRBni up- and down- convert instructions, a software texture sampler would be a lot more feasible.
    - coherentpony 12y ago
      Does gcc support these new wider registers yet?
azurelogic 12y ago
The author is complaining out of context on a couple of points here: 1) The B820 came out 1.25 years later than the B940. So, it's not hard to see that maybe Intel decided in that timeframe to add VT-x support. 2) None of the K-series CPUs support VT-d. For some reason, VT-d and overclocking are not compatible. This would have been more noticeable if, for example, the author had compared the i7-4770K to the i7-4770, not the i5-4570. The same distinction is there between the i5-4670 and i5-4670K. 3) The table is organized in a misleading fashion. Why put the weakest CPUs in the center except to make proper trend be intentionally disrupted After fixing or striking these issues, this isn't even an article worth writing because the features suddenly make sense.
- wtallis 12y ago
  > "None of the K-series CPUs support VT-d. For some reason, VT-d and overclocking are not compatible." No, compatible usually implies there's a technological or engineering justification. This is pure marketing. And the Devils Canyon update to Haswell introduced some -K parts that have VT-d. Edit: And support likewise implies that even if it's not a purely technical issue, that there's at least some tradeoff. Enabling virtualization has a price to the consumer, but doesn't cost Intel anything extra.
- binarycrusader 12y ago
  Not true. The 4790k supports vt-d. All indications are that it's a market segmentation choice Intel made.
jandrewrogers 12y ago
There is a pervasive issue in that most code written today is tacitly designed for the assumptions of microarchitectures from a decade ago, and most code is even older and is rarely rewritten. Generally speaking, compilers have a limited ability to improve the basic design of code or deviate from the assumptions about hardware embedded in that code. More often than not, taking advantage of different microarchitectures is not just about the code generation, it is also about algorithm design and selection, which falls directly on the programmer. I currently design software that assumes the Haswell microarchitecture. While the code is written in C++ and the high level architecture is generally the same, the lower level idioms are different because they reflect the strength of the microarchitecture. If the code was for the latest ARM core, it would need to be quite different to be efficient. And I am not even talking about things like AVX2. Idiom changes to match microarchitectures are not "micro-optimizations" in the traditional sense; it will often buy 2x performance improvement overall versus well designed generic code tacitly optimized for another microarchitecture. The reality is that almost no one writes code for e.g. the Haswell microarchitecture. The idea of writing code for a microarchitecture at the level of, say, C++ does not even enter most programmers' minds. Broadly speaking, a compiler will not allow you to take advantage of advancements in microarchitecture except by accident, which works sometimes but is not efficient in terms of return on the new microarchitecture. Compilers learn some micro-idioms, but most of the macro-idioms escape them (like designing algorithms for the ALU parallelism of a particular microarchitecture). The last big microarchitecture change for Intel was Nehalem, the original "i7". A lot of code optimization assumptions from prior CPUs went out the window with that microarchitecture. The latest, Haswell, added more usable ALU parallelism and the BMI2 extensions, which are quite useful if you know how to exploit them but nothing Earth-shattering. AVX2 was nice, but too limited to have much value for most normal code. That said, I am pretty excited about AVX-512, which will be a major microarchitecture extension once that it is available. The giant caveat is that no one will be able to really take advantage of it without, once again, redesigning their code for that microarchitecture. A compiler won't be able to do that for you, which has been the real stumbling block for the adoption of advanced features in new microarchitectures. What constitutes an optimal algorithm or data structure is microarchitecture dependent.
- hdevalence 12y ago
darklajid 12y ago
Trying to buy me a present atm, new desktop machine. This is actually one of my pain points, because none of the sites I visit list cpu features and I am interested in some (notably virtualization related extensions).
- ivank 12y ago
  Intel publishes this information for every CPU they make at http://ark.intel.com/ http://ark.intel.com/
antonios 12y ago
Strangely enough, ECC is supported on some Core i3 models.
DSingularity 12y ago
I don't think a lot of people understand that some of these features need more than a clear chicken bit. Some chips can be incompatible with features due to physical reasons. Other of these features make little sense for some chips and some markets. For example, some of the VTd features. The majority of personal users aren't scheduling more than one or two VMs max. Do we really need VPID and larger TLBs for such workloads? No. So why include the feature? If binary size becomes an issue then we need a better solution. Maybe its delaying some or all optimization for install time. Maybe its providing individual binaries for different targets.
- wtallis 12y ago
  VT-d is branded as a virtualization feature, but it's also a killer security feature. It should be treated as a hard requirement for any system that has DMA-capable external interfaces like Firewire or Thunderbolt. It can be used to protect the system from exploits that run on the GPU or any of the other processors that are included in peripheral devices. But nobody's going to completely redesign the driver model of their OS if only 3% of their users can reap the benefits.
  - DSingularity 12y ago
    I actually never thought of it from that perspective. Can you expand on this? Is the primary threat DOS or malicious DMA ops from external interfaces and devices and the primary advantage mitigation by rerouting I/O from that device to a "null" VM?
- nkurz 12y ago
  Some chips can be incompatible with features due to physical reasons I think this is good point. So far, I think the AVX/AVX2 distinction is based only on release date --- the newer chips support the newer instruction set. This is a good sort of improvement. And it's probably only practical to support AVX and AVX2 if you have 256-bit registers to work with. Does the lower end mobile Pentium branded line even have full physical support for 256-bit vectors? That is, are they supporting 128-bit SSE instructions in a full 256-bit register but not providing any instructions that use the upper lane?

116 points by shodanshok 12y ago

Moore's law is over. Pentium 4s reached 3GHZ 15 years ago. CPUs try things like parallelizing while the human brain thinks sequentially. CPUs are still getting faster but at an incrementally slower rate. A 4 year old Macbook Air is half as performant as the latest. In previous decades, the performance gains were 2-5X per year. A paradigm shift (quantum computing?) needs to happen soon so computation can continue scaling.

nemothekid 12y ago
Moore's law was never about performance.
- billions 12y ago
  Moore's law is about the number of transistors on a chip which is reaching a limit because heat cannot be dissipated fast enough. Heat is the primary limit on performance.
  - sliverstorm 12y ago
    More transistors is still better, even if they need to be off most of the time. You can spend more silicon on advanced features, just like AVX, spending transistor count for performance at neutral power cost.
Zigurd 12y ago
The illusion of the Cartesian theater is seemingly sequential. Your brain is not.
- billions 12y ago
  Here's a bit more on linear thinking: http://en.wikipedia.org/wiki/Cocktail_party_effect http://en.wikipedia.org/wiki/Cocktail_party_effect *Feel free to send more insults my way if it fulfills your ego. I am here to listen, but please keep the discussion constructive for the sake of the community.
DigitalJack 12y ago
"In previous decades, the performance gains were 2-5X per year." What decade was that? According to this[1], it's never been better than ~50% year over year. [1] http://www.cs.columbia.edu/~sedwards/classes/2012/3827-spring/advanced-arch-2011.pdf http://www.cs.columbia.edu/~sedwards/classes/2012/3827-sprin...

hayksaakian 12y ago

I've noticed that CPU companies are focusing more and more on power efficiency to compete with ARM potentially. Maybe turning off the features described in the OP makes lower end CPUs run faster? That might be significant since i also presume most laptops use those same lower end CPUs. Laptops being the ones that need to save energy much of the time. (Desktops are obviously plugged in). This is probably most significant in the Microsoft Surface (it uses a real intel CPU if i recall correctly). I wonder which features it has marked "off" , and what impact that has on battery power.

icegreentea 12y ago
The "lowest" end of the CPUs that the OP discusses are low end desktop/laptop parts. Furthermore, the biggest criticism of the author isn't the feature disabling per se, but how inconsistently Intel applies it across their overall performance bins. For example, the lack of TXT support in high end i7 parts when its there for middle tier i5 parts. Why the i7-3990K has VT-d and the i7-3770K doesnt(which really should just be distinguished by their clock/cache/TDP).
- ptysiu 12y ago
  3770K cpu has basic version 3770, which has the VT-d ext. There is no such thing like 3990k.
wtallis 12y ago
Remember, within a generation these chips are almost all made from the same set of masks. None of these disabled features save any transistors or die area; the disabling just leaves you with a dead spot on the chip. So the real question is if you've got the hardware in place to provide these special features, can you save any power by not using those features? The answer is that you only save power by not doing at all the things those features accelerate. It's never more efficient to implement AES through general-purpose instructions than using the fixed-function hardware. If you've got a workload that can benefit from the wider SIMD units, it won't save any energy to only use the narrower instructions. If you're trying to secure or virtualize your OS, doing it with VT-x and VT-d will be so much faster than emulating it in software that even if those features added several watts to the chips power consumption you would still save energy. Doing less can save power, but doing the same amount of stuff the hard way doesn't help anything.

ChuckMcM 12y ago

The author makes a point, when CPUs are "good enough" its a real problem for CPU manufacturers. They don't price them to have a service life of 15 years, they expect them to be replaced every 2 - 3 years. And the option there is to featurize them. It is interesting to watch in the ARM space as well.

nkurz 12y ago

As someone excited by the improvements that are possible moving from AVX to AVX2, I was recently surprised to learn that Intel has chips released this year that do not support AVX. AVX-512 is still supposedly scheduled for release next year with Skylake. How long do you suppose until it's reasonable to presume that most processors will support it? SSE 4.2 came out in 2008 and appears to be the baseline now, so 5 years seems like a reasonable guess. It's hard to believe this degree of ISA segmentation is going to benefit Intel in the end.

wtallis 12y ago
I think that the SIMD instructions are well past the point of diminishing returns, both for the kinds of instructions provided and the width of the vectors. I'm more interested in how VT-d and TSX allow different software architectures, if and only if you can design your OS around the assumption that they're available. By only including them on select models, Intel's making them much less useful even for the customers who want to pay extra to have those features.
- thechao 12y ago
  I used to write software rasterizers in a past life. AVX-512 is straight-up an observed 8x performance gain over SSE: a well-written software rasterizer is a very clever thread-scheduling algorithm wrapped around long lists of FMA-load/store sequences. I know that ray-tracers, databases, and other 'big data' all gain equally-well from AVX-512. The IO-request depth on these new parts is such that, for ALU-heavy work, with good IO-spread, memory latency is completely hidden---fetch time is still ~250-300c, but you just no longer see it. The only thing I miss is 'addsets', which was dropped from LRBni, as this instruction was 'the rasterizer function': it now requires a fairly involved sequence to replicate in AVX-512. Pining for other lost things: if we had the LRBni up- and down- convert instructions, a software texture sampler would be a lot more feasible.
  - coherentpony 12y ago
    Does gcc support these new wider registers yet?

azurelogic 12y ago

The author is complaining out of context on a couple of points here: 1) The B820 came out 1.25 years later than the B940. So, it's not hard to see that maybe Intel decided in that timeframe to add VT-x support. 2) None of the K-series CPUs support VT-d. For some reason, VT-d and overclocking are not compatible. This would have been more noticeable if, for example, the author had compared the i7-4770K to the i7-4770, not the i5-4570. The same distinction is there between the i5-4670 and i5-4670K. 3) The table is organized in a misleading fashion. Why put the weakest CPUs in the center except to make proper trend be intentionally disrupted After fixing or striking these issues, this isn't even an article worth writing because the features suddenly make sense.

wtallis 12y ago
> "None of the K-series CPUs support VT-d. For some reason, VT-d and overclocking are not compatible." No, compatible usually implies there's a technological or engineering justification. This is pure marketing. And the Devils Canyon update to Haswell introduced some -K parts that have VT-d. Edit: And support likewise implies that even if it's not a purely technical issue, that there's at least some tradeoff. Enabling virtualization has a price to the consumer, but doesn't cost Intel anything extra.
binarycrusader 12y ago
Not true. The 4790k supports vt-d. All indications are that it's a market segmentation choice Intel made.

jandrewrogers 12y ago

There is a pervasive issue in that most code written today is tacitly designed for the assumptions of microarchitectures from a decade ago, and most code is even older and is rarely rewritten. Generally speaking, compilers have a limited ability to improve the basic design of code or deviate from the assumptions about hardware embedded in that code. More often than not, taking advantage of different microarchitectures is not just about the code generation, it is also about algorithm design and selection, which falls directly on the programmer. I currently design software that assumes the Haswell microarchitecture. While the code is written in C++ and the high level architecture is generally the same, the lower level idioms are different because they reflect the strength of the microarchitecture. If the code was for the latest ARM core, it would need to be quite different to be efficient. And I am not even talking about things like AVX2. Idiom changes to match microarchitectures are not "micro-optimizations" in the traditional sense; it will often buy 2x performance improvement overall versus well designed generic code tacitly optimized for another microarchitecture. The reality is that almost no one writes code for e.g. the Haswell microarchitecture. The idea of writing code for a microarchitecture at the level of, say, C++ does not even enter most programmers' minds. Broadly speaking, a compiler will not allow you to take advantage of advancements in microarchitecture except by accident, which works sometimes but is not efficient in terms of return on the new microarchitecture. Compilers learn some micro-idioms, but most of the macro-idioms escape them (like designing algorithms for the ALU parallelism of a particular microarchitecture). The last big microarchitecture change for Intel was Nehalem, the original "i7". A lot of code optimization assumptions from prior CPUs went out the window with that microarchitecture. The latest, Haswell, added more usable ALU parallelism and the BMI2 extensions, which are quite useful if you know how to exploit them but nothing Earth-shattering. AVX2 was nice, but too limited to have much value for most normal code. That said, I am pretty excited about AVX-512, which will be a major microarchitecture extension once that it is available. The giant caveat is that no one will be able to really take advantage of it without, once again, redesigning their code for that microarchitecture. A compiler won't be able to do that for you, which has been the real stumbling block for the adoption of advanced features in new microarchitectures. What constitutes an optimal algorithm or data structure is microarchitecture dependent.

hdevalence 12y ago

darklajid 12y ago

Trying to buy me a present atm, new desktop machine. This is actually one of my pain points, because none of the sites I visit list cpu features and I am interested in some (notably virtualization related extensions).

ivank 12y ago
Intel publishes this information for every CPU they make at http://ark.intel.com/ http://ark.intel.com/

antonios 12y ago

Strangely enough, ECC is supported on some Core i3 models.

DSingularity 12y ago

I don't think a lot of people understand that some of these features need more than a clear chicken bit. Some chips can be incompatible with features due to physical reasons. Other of these features make little sense for some chips and some markets. For example, some of the VTd features. The majority of personal users aren't scheduling more than one or two VMs max. Do we really need VPID and larger TLBs for such workloads? No. So why include the feature? If binary size becomes an issue then we need a better solution. Maybe its delaying some or all optimization for install time. Maybe its providing individual binaries for different targets.

wtallis 12y ago
VT-d is branded as a virtualization feature, but it's also a killer security feature. It should be treated as a hard requirement for any system that has DMA-capable external interfaces like Firewire or Thunderbolt. It can be used to protect the system from exploits that run on the GPU or any of the other processors that are included in peripheral devices. But nobody's going to completely redesign the driver model of their OS if only 3% of their users can reap the benefits.
- DSingularity 12y ago
  I actually never thought of it from that perspective. Can you expand on this? Is the primary threat DOS or malicious DMA ops from external interfaces and devices and the primary advantage mitigation by rerouting I/O from that device to a "null" VM?
nkurz 12y ago
Some chips can be incompatible with features due to physical reasons I think this is good point. So far, I think the AVX/AVX2 distinction is based only on release date --- the newer chips support the newer instruction set. This is a good sort of improvement. And it's probably only practical to support AVX and AVX2 if you have 256-bit registers to work with. Does the lower end mobile Pentium branded line even have full physical support for 256-bit vectors? That is, are they supporting 128-bit SSE instructions in a full 256-bit register but not providing any instructions that use the upper lane?