3 ms·
The reason the chips will be slower in practice is because they are produced in small batches, and need to be produced by smaller fabs and by extension much old
by sspiff 12y ago
The reason the chips will be slower in practice is because they are produced in small batches, and need to be produced by smaller fabs and by extension much older process. MIPS is routinely produced at 95nm still.
- arbuge 12y agoMOSIS offers multi-project wafer (MPW) runs at 28nm from GlobalFoundries. https://www.mosis.com/products https://www.mosis.com/products
- asb 12y agoWe at lowRISC intend to produce in volume at 40nm or 28nm. http://www.lowrisc.org/ http://www.lowrisc.org/
- arbuge 12y agoLooks really interesting. Where are you guys based? Cambridge, UK I'm guessing?
- asb 12y agoYes, the core team is based in Cambridge, UK. However we do intend to be a truly open-source project, with an open and distributed development process which would involve arbitrarily geographically distributed third-party contributors.
- sspiff 12y agoThat's truly great to hear!
- alain94040 12y agoYes, and the fact that most of the performance comes from the micro-architecture. CPU design is all about the tradeoff between size, complexity, speed and power consumption. New RISC architectures tend to start on the low-end of the scale (clean architecture, short pipeline, small die), and if they are successful, move toward the x86/ugly/big/complex/fast spot.