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Does anyone have actual experience using RISC-V? It does come with a gcc toolchain, so it should just run C - but is it of any practical use yet, relative to th
by JoachimSchipper 12y ago
Does anyone have actual experience using RISC-V? It does come with a gcc toolchain, so it should just run C - but is it of any practical use yet, relative to the enormous ARM (or MIPS, or even SPARC) ecosystem?
- qwerta 12y agoWe were investigating CPUs for embedded use. I am not sure right now if it was RISC or MIPS. The performance was fraction of ARM or x86. But the consulting company would build SOC exactly to our spec. There were zero licensing fees. So for embedded use if performance is not important, I would seriously consider it.
- arbuge 12y agoReading the article, I see no reason why there should be any major performance issues inherent to RISC-V. Lack of an ecosystem looks like the issue, at least initially. But a $1m licensing fee for a CPU with an established ecosystem is an issue too...
- sspiff 12y agoThe reason the chips will be slower in practice is because they are produced in small batches, and need to be produced by smaller fabs and by extension much older process. MIPS is routinely produced at 95nm still.
- arbuge 12y agoMOSIS offers multi-project wafer (MPW) runs at 28nm from GlobalFoundries. https://www.mosis.com/products https://www.mosis.com/products
- asb 12y agoWe at lowRISC intend to produce in volume at 40nm or 28nm. http://www.lowrisc.org/ http://www.lowrisc.org/
- arbuge 12y agoLooks really interesting. Where are you guys based? Cambridge, UK I'm guessing?
- asb 12y agoYes, the core team is based in Cambridge, UK. However we do intend to be a truly open-source project, with an open and distributed development process which would involve arbitrarily geographically distributed third-party contributors.
- sspiff 12y agoThat's truly great to hear!
- alain94040 12y agoYes, and the fact that most of the performance comes from the micro-architecture. CPU design is all about the tradeoff between size, complexity, speed and power consumption. New RISC architectures tend to start on the low-end of the scale (clean architecture, short pipeline, small die), and if they are successful, move toward the x86/ugly/big/complex/fast spot.
- zhemao 12y agoIf you have a Xilinx FPGA, you can program our newly released Rocket core onto it and play around. https://github.com/ucb-bar/rocket-chip https://github.com/ucb-bar/rocket-chip We don't have a production-quality SoC out, so "practical use" is still a ways away.
- ash 12y agoIn your opinion, is it a good idea to replace ZPU with Rocket on Xilinx FPGA? What are advantages and disadvantages? http://opensource.zylin.com/zpu.htm http://opensource.zylin.com/zpu.htm
- zhemao 12y agoThe ZPU is designed to use as few FPGA resources as possible. So if you're looking for something to just do a little bit of control logic to tie things together, it probably is the way to go. Rocket on the other hand is a full-fledged in-order core with hardware mutliplier, single-precision and double-precision floating-point units, and MMU. Therefore, it can do things like boot a full Linux kernel, which the ZPU cannot. Rocket also has the RoCC co-processor interface, which allows you to define your own ISA extensions in Chisel.