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> taking the increased transistor budget and improving those existing four cores There is not much space for improvement left. ILP had been stagnating quite fo
by sklogic 12y ago
> taking the increased transistor budget and improving those existing four cores
There is not much space for improvement left. ILP had been stagnating quite for a while, and there is no hope of improvement with the current ISAs. More OoO-friendly ISAs are being developed, but are unlikely to hit the market any time soon.
Caches are also approaching the upper limit, and for the bigger caches we need either some much smarter cache management techniques (explicit prefetching, etc.), or a totally different programming model (e.g., using a flat scratchpad memory explicitly instead of transparent caches).
Core count grows for a reason - there is not really much stuff we can put into a single core any further, not without breaking the whole architecture.
- ghshephard 12y agoIn order to utilize those increased cores, though, developers will need to write code that can take advantage of them. Is there any indication of that happening? That's the second angle on this - even though writing parallel/concurrent code might in theory improve performance, it won't help if people continue to write single-threaded applications for everything except IO/Graphics. I.E. It might be still more useful to build bigger 4-core processors, simply because all the developers and code out there are designed to take advantage of them - and a theoretically better 6-core processor would just end up with 2-3 cores always idling.
- sklogic 12y ago> developers will need to write code that can take advantage of them In the said case of parallel compilation of, say, JS, it's only a tiny minority of the developers who need to be able to do so. > It might be still more useful to build bigger 4-core processors It would have been great if we could build any bigger cores. Unfortunately, there is not much scope for improvement left, not unless we ditch the existing ISAs and programming models.