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Cortex M0+ is 12k gates in it's smallest configuration according to http://www.arrownac.com/offers/nxp-semiconductors/cortex/cortex-m0-article.pdf http://www.ar

by pja 12y ago

Cortex M0+ is 12k gates in it's smallest configuration according to http://www.arrownac.com/offers/nxp-semiconductors/cortex/cortex-m0-article.pdf http://www.arrownac.com/offers/nxp-semiconductors/cortex/cor... This page quotes a Cortex M4 announcement press release (which I can't find) which says that a stock M4 (without FPU/DSP instruction support) comes in at 65k gates. Meanwhile this pdf: http://www.mcu-related.com/architectures/35-cortex-m3/96-cortex-m4 http://www.mcu-related.com/architectures/35-cortex-m3/96-cor... claims that an M3 comes in at 43k gates. The main difference between the two is a 32x32+64 into 64 multiplier for DSP use plus some SIMD instructions so your estimate for the multiplier seems to be in the right ballpark!

ctz 12y ago
Counting gates vs transistors is about a factor of four or more difference.
- pja 12y ago
  You're right, I'd missed that - I imagine that would probably explain the confusion in the parent post then!
  - rasz_pl 12y ago
    yes. Got it all mixed up, was thinking m68k is same size as m4, and later somehow m68k became 8051 and gates transistors :(
bsder 12y ago
That's better. 65K gates is probably close to 240K transistors. And an 8051 is probably close to 5K transistors, not 60K transistors.