4 ms·

atmel recently announced a cortex-m0 with 40ua/MHz which is competitive with 8-bit , and energy micro chips are also very competitive using their smart peripher

by minthd 12y ago

atmel recently announced a cortex-m0 with 40ua/MHz which is competitive with 8-bit , and energy micro chips are also very competitive using their smart peripherals .

teraflop 12y ago
Wow. To put that in perspective, I found a reference [1] saying the simplest Cortex-M0 chips have about 12K gates, which means that the processor uses about 20,000 electrons per cycle, per gate. When you think about how many orders of magnitude of improvement there have been since the dawn of computing, it's astonishing to realize that there might not be too many left before we start hitting the fundamental limits of semiconductors. [1]: http://www.arrownac.com/offers/nxp-semiconductors/cortex/cortex-m0-article.pdf http://www.arrownac.com/offers/nxp-semiconductors/cortex/cor...
- minthd 12y ago
  Maybe there's a possibility to totally turn parts of the core on and off on instruction-by instruction basis - to the point where for each instruction ,you'll only have the logic responsible for it turned on ?
  - williadc 12y ago
    At that point, the power controller would be as complex as your application processor, and you'd be trying to figure out how to power gate some of its features.
    - minthd 12y ago
      Ok maybe instruction by instruction is a bit too much, But you could simple divide the core to many power areas(say 32), and before each code section, let a compiler set the optimal power gating for it by writing a 32 bit value. I'm sure such an arrangement would get most of the power efficiency, with minimal complexity in the mcu.
      - Sanddancer 12y ago
        A lot of micros already do that, with various levels of sleep, and lots and lots of i/o driven interrupts to wake up the processor when relevant data needs managed. What this ends up as is your processors main function sets up the proc, and then runs a loop that consists of little more than while(1) { sleep(); }. When some state changes that needs CPU time, it'll raise an interrupt, the interrupt handler will do what's needed, and the proc will go back to sleep. Micros have a lot of smart, low power peripheral processing available to them that helps keep power consumption even lower.
        minthd 12y ago
        You're talking about smart autonomous peripherals.They're great,but if you need to run arbitrary code(or have the design more portable),you'll need to use the core, so it's valuable to have a similar fine grained power-gating applied to the core.
  - rasz_pl 12y ago
    asynchronous processors, been on the table for over 10 years (if not 20) http://www.design-reuse.com/articles/35659/8-bit-pipelined-asynchronous-processor-core.html http://www.design-reuse.com/articles/35659/8-bit-pipelined-a...

by minthd 12y ago

atmel recently announced a cortex-m0 with 40ua/MHz which is competitive with 8-bit , and energy micro chips are also very competitive using their smart peripherals .

teraflop 12y ago

Wow. To put that in perspective, I found a reference [1] saying the simplest Cortex-M0 chips have about 12K gates, which means that the processor uses about 20,000 electrons per cycle, per gate. When you think about how many orders of magnitude of improvement there have been since the dawn of computing, it's astonishing to realize that there might not be too many left before we start hitting the fundamental limits of semiconductors. [1]: http://www.arrownac.com/offers/nxp-semiconductors/cortex/cortex-m0-article.pdf http://www.arrownac.com/offers/nxp-semiconductors/cortex/cor...

minthd 12y ago
Maybe there's a possibility to totally turn parts of the core on and off on instruction-by instruction basis - to the point where for each instruction ,you'll only have the logic responsible for it turned on ?
- williadc 12y ago
  At that point, the power controller would be as complex as your application processor, and you'd be trying to figure out how to power gate some of its features.
  - minthd 12y ago
    Ok maybe instruction by instruction is a bit too much, But you could simple divide the core to many power areas(say 32), and before each code section, let a compiler set the optimal power gating for it by writing a 32 bit value. I'm sure such an arrangement would get most of the power efficiency, with minimal complexity in the mcu.
    - Sanddancer 12y ago
      A lot of micros already do that, with various levels of sleep, and lots and lots of i/o driven interrupts to wake up the processor when relevant data needs managed. What this ends up as is your processors main function sets up the proc, and then runs a loop that consists of little more than while(1) { sleep(); }. When some state changes that needs CPU time, it'll raise an interrupt, the interrupt handler will do what's needed, and the proc will go back to sleep. Micros have a lot of smart, low power peripheral processing available to them that helps keep power consumption even lower.
      - minthd 12y ago
        You're talking about smart autonomous peripherals.They're great,but if you need to run arbitrary code(or have the design more portable),you'll need to use the core, so it's valuable to have a similar fine grained power-gating applied to the core.
- rasz_pl 12y ago
  asynchronous processors, been on the table for over 10 years (if not 20) http://www.design-reuse.com/articles/35659/8-bit-pipelined-asynchronous-processor-core.html http://www.design-reuse.com/articles/35659/8-bit-pipelined-a...