4 ms·
Yeah, looks like it's for function alignment padding. It's a pretty common thing at the end of functions to have the next function start on a specific boundary
by cjubb39 12y ago
Yeah, looks like it's for function alignment padding. It's a pretty common thing at the end of functions to have the next function start on a specific boundary. (even if the first function doesn't fall into the other)
I haven't tested, but I'd bet good money that 12 NOPs would be faster than a jmp.
- pkhuong 12y agoLong nops would be marginally quicker.
- deleted 12y ago[deleted]
- pbsd 12y agoYou can do an unconditional jump every 1 or 2 cycles, depending on the chip, whereas no chip I know of can execute more than 4 nops per cycle. Therefore I would say the jump is probably marginally faster than 12 nops. Smart toolchains will turn those 12 bytes into 2 multi-byte nops, e.g., a 9-byte one and a 3-byte one.
- 0x0 12y agoWhat does a 9byte NOP look like?
- pbsd 12y agonop word ptr [eax+eax+0] ; 66 0f 1f 84 00 00 00 00 00
- pkhuong 12y agohttps://github.com/sbcl/sbcl/blob/master/src/compiler/x86-64/insts.lisp#L2978 https://github.com/sbcl/sbcl/blob/master/src/compiler/x86-64... has 0x66 0x0f 0x1f 0x84 0x00 0x00 0x00 0x00 0x00 That's a size override prefix, followed by the dedicated NOP instruction (0x0f 0x1f), and finally 6 bytes to encode an effective address with offset.
- makomk 12y agoMulti-byte nops have compatibility issues on some of the more obscure 32-bit x86 CPUs, unfortunately: https://sourceware.org/bugzilla/show_bug.cgi?id=13675 https://sourceware.org/bugzilla/show_bug.cgi?id=13675
- pkhuong 12y agoRight… you have to check cpuid for the long nop feature. I believe 0x66 0x90 is compatible (but slow, I would expect) with older CPUs.
- danielweber 12y agoDo JMPs invalidate caches? That was the story I was telling myself where 12 NOPs would be faster than JMPing; I don't know if it's true.
- jlebar 12y agoLoops can be implemented with JMPs, and it would be Very Bad if every iteration of a loop invalidated caches. (In fact, it would be Very Bad if just about anything common invalidated caches, given how important they are to modern CPU performance.)
- pbsd 12y agoI don't know what exactly you mean by that, but I'm going with no. Unconditional jumps do interact with the uops cache in recent Intel chips, but they do so by terminating the current uops cache line---which is generally desirable.